Semiconductor device including capacitive circuit and short-circuit preventing circuit connected in series
View Patent ↗In a semiconductor circuit device including a first terminal adapted to receive a first voltage and a second terminal adapted to receive a second voltage lower than the first voltage, a capacitive circuit and a short-circuit preventing circuit are provided in series between the first and second terminals. In this case, when the capacitive element is in an insulating (non-conductive) state, the short-circuit preventing circuit is in a conductive state, while, when the capacitive circuit is in a conductive state, the short-circuit preventing circuit is in an insulating state.
1. A semiconductor circuit device comprising:
a first terminal adapted to receive a first voltage;
a second terminal adapted to receive a second voltage lower than said first voltage; and
a capacitive circuit and a short-circuit preventing circuit provided in series between said first and second terminals,
wherein, when said capacitive circuit is in an insulating state, said short-circuit preventing circuit is in a conductive state, while, when said capacitive circuit is in a conductive state, said short-circuit preventing circuit is in an insulating state,
wherein said short-circuit preventing circuit comprises an n-channel enhancement-type MOS transistor provided between said first terminal and said capacitive circuit,
wherein said n-channel enhancement-type MOS transistor has a gate connected to one electrode of said capacitive circuit and a backgate connected to said second terminal, and
wherein another electrode of said capacitive circuit is connected to said second terminal.
2. The semiconductor circuit device as set forth in claim 1 , wherein said first terminal comprises a power supply terminal and said second terminal comprises a ground terminal.
3. The semiconductor circuit device as set forth in claim 1 , wherein said capacitive circuit comprises at least one capacitive element.
4. The semiconductor circuit device as set forth in claim 2 , wherein said capacitive element is of a MOS type.
5. The semiconductor circuit device as set forth in claim 2 , wherein said capacitive element serves as a decoupling capacitor.
6. A semiconductor circuit device comprising:
a first terminal adapted to receive a first voltage;
a second terminal adapted to receive a second voltage lower than said first voltage; and
a capacitive circuit and a short-circuit preventing circuit provided in series between said first and second terminals,
wherein, when said capacitive circuit is in an insulating state, said short-circuit preventing circuit is in a conductive state, while, when said capacitive circuit is in a conductive state, said short-circuit preventing circuit is in an insulating state,
wherein said short-circuit preventing circuit comprises
a p-channel enhancement-type MOS transistor provided between said capacitive circuit and said second terminal,
wherein said p-channel enhancement-type MOS transistor has a gate connected to one electrode of said capacitive circuit and a backgate connected to said first terminal, and
wherein another electrode of said capacitive element is connected to said first terminal.
7. A semiconductor circuit device comprising:
a first terminal adapted to receive a first voltage;
a second terminal adapted to receive a second voltage lower than said first voltage; and
a plurality of pairs of one capacitive circuit and one short-circuit preventing circuit provided in series between said first and second terminals,
wherein, when said capacitive circuit of a respective one of said pairs is in an insulating state, said short-circuit preventing circuit of the respective one of said pairs is in a conductive state, while, when said capacitive circuit of the respective one of said pairs is in a conductive state, said short-circuit preventing circuit of the respective one of said pairs is in an insulating state,
wherein said short-circuit preventing circuit comprises an n-channel enhancement-type MOS transistor provided between said first terminal and said capacitive circuit,
wherein said n-channel enhancement-type MOS transistor has a gate connected to one electrode of said capacitive circuit and a backgate connected to said second terminal, and
wherein another electrode of said capacitive circuit is connected to said second terminal.
8. The semiconductor circuit device as set forth in claim 7 , wherein said first terminal comprises a power supply terminal and said second terminal comprises a ground terminal.
9. The semiconductor circuit device as set forth in claim 7 , wherein said capacitive circuit comprises at least one capacitive element.
10. The semiconductor circuit device as set forth in claim 9 , wherein said capacitive element is of a MOS type.
11. The semiconductor circuit device as set forth in claim 9 , wherein said capacitive element serves as a decoupling capacitor.
12. A semiconductor circuit device comprising:
a first terminal adapted to receive a first voltage;
a second terminal adapted to receive a second voltage lower than said first voltage; and
a plurality of pairs of one capacitive circuit and one short-circuit preventing circuit provided in series between said first and second terminals,
wherein, when said capacitive circuit of a respective one of said pairs is in an insulating state, said short-circuit preventing circuit of the respective one of said pairs is in a conductive state, while, when said capacitive circuit of the respective one of said pairs is in a conductive state, said short-circuit preventing circuit of the respective one of said pairs is in an insulating state,
wherein said short-circuit preventing circuit comprises
a p-channel enhancement-type MOS transistor provided between said capacitive circuit and said second terminal,
wherein said p-channel enhancement-type MOS transistor has a gate connected to one electrode of said capacitive circuit and a backgate connected to said first terminal, and
wherein another electrode of said capacitive circuit is connected to said first terminal.