Memory test circuit and method

1. A memory test circuit, comprising:

a testing unit testing a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory;

a test pattern generating circuit generating a test pattern corresponding to the pattern mode signal; and

a storage unit storing the pattern mode signal as failure information.

2. The memory test circuit according to claim 1 , wherein the testing unit includes:

an expected value generating circuit generating an expected value in accordance with the pattern mode signal; and

an expected value comparator circuit comparing output data from the memory with an expected value generated with the expected value generating circuit, and

the storage unit includes a failure information storage circuit storing failure information detected with the expected value comparator circuit together with the pattern mode signal.

3. The memory test circuit according to claim 1 , further comprising:

a counter counting the number of actions constituting the sub-test pattern,

wherein the storage unit includes a failure information storage circuit, and the failure information storage circuit stores a count value corresponding to a failure detected with an expected value comparator circuit as the failure information.

4. The memory test circuit according to claim 1 , further comprising:

a storage determining circuit determining whether or not failure information detected with an expected value comparator circuit is stored in a failure information storage circuit in accordance with preset failure information storage method information.

5. The memory test circuit according to claim 1 , wherein a failure information storage method information includes information designating failure information to be stored out of detected failure information by specifying an ordinal position from a detection start position, and

a storage determining circuit stores failure information corresponding to the ordinal position in the failure information storage circuit.

6. The memory test circuit according to claim 1 , wherein failure information storage method information includes information designating an address of failure information to be stored out of the detected failure information as a condition, and

a storage determining unit stores failure information corresponding to the condition in the failure information storage circuit.

7. A memory test circuit, comprising:

a failure information detecting circuit detecting failure information of a memory;

a failure information storage circuit; and

a storage determining circuit determining whether or not failure information detected with the failure information detecting circuit is stored in the failure information storage circuit based on preset failure information storage method information, and the failure information storage circuit includes a flag storage circuit, whereby if the number of failure information exceeds the number of storable failure information, a value representing that the number of failure information exceeds the number of storable failure information is stored in the flag storage circuit.

8. The memory test circuit according to claim 7 , wherein the failure information storage method information includes information designating failure information to be stored out of the detected failure information by specifying an ordinal position from a detection start position, and

the storage determining circuit stores failure information corresponding to the ordinal position in the failure information storage circuit.

9. The memory test circuit according to claim 7 , wherein the failure information storage method information includes information designating an address of failure information to be stored out of the detected failure information as a condition, and

the storage determining circuit stores failure information corresponding to the condition in the failure information storage circuit.

10. A memory test method, comprising:

generating a test pattern corresponding to a pattern mode signal designating a sub-test pattern included in the test pattern and including a plurality of test actions for the memory;

executing a test on a memory in accordance with the test pattern corresponding to the pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory; and

storing the pattern mode signal as failure information.

11. A memory test method, comprising:

detecting failure information of a memory;

determining whether or not to store the detected failure information in accordance with preset failure information storage method information, and

if the number of failure information exceeds the number of storable failure information, setting a value representing that the number of failure information exceeds the number of storable failure information in a flag of a storage circuit.