Apparatus and method for over-voltage, under-voltage and over-current stress protection for transceiver input and output circuitry

1. A pre-driver circuit, comprising:

first and second transistors forming a differential pair and driven by a differential input voltage;

a third transistor connected between sources of the first and second transistors and a ground;

first and second resistors connected to drains of the first and second transistors, respectively;

a fourth transistor connected between a power supply voltage and the first and second resistors; and

fifth and sixth transistors connected in series between the power supply voltage and the first and second resistors,

wherein a node between the fifth and sixth transistors is connected to a gate of the fourth transistor.

2. The circuit of claim 1 , further comprising:

third, fourth, and fifth resistors connected in series with a seventh transistor and between the power supply and the ground, wherein a node between the third and fourth resistors is connected to a gate of the fifth transistor.

3. The circuit of claim 1 , further comprising:

sixth and seventh resistors connected in series with an eighth transistor between the power supply and the ground, wherein a node between the sixth and seventh resistors is connected to a gate of the sixth transistor.

4. The circuit of claim 3 , further comprising:

an eighth resistor in parallel with the fifth resistor and the seventh transistor, wherein a node between the fourth and fifth resistors is connected to a gate of the eighth transistor.

5. The circuit of claim 4 , further comprising:

a ninth resistor in parallel with the seventh resistor and the eighth transistor.

6. The circuit of claim 5 , further comprising:

tenth and eleventh resistors connected in series with ninth and tenth transistors between the power supply and the ground;

twelfth and thirteenth resistors connected in series with eleventh and twelfth transistors between the power supply and the ground;

a fourteenth transistor connected between a node between the twelfth and thirteen resistors and a node between the second resistor and the second transistor; and

a fifteenth transistor connected between the node between the twelfth and thirteen resistors and a node between the first resistor and the first transistor.

7. The circuit of claim 6 , wherein gates of the fourteenth and fifteenth transistors are connected to a node between the tenth and eleventh resistors.

8. The circuit of claim 7 further comprising:

fourteenth and fifteenth resistors connected in series between the power supply and the ground, wherein a node between the fourteenth and fifteenth resistors is connected to gates of the ninth and eleventh transistors.

9. The circuit of claim 8 , further comprising:

a sixteenth transistor in series with a current source for biasing the third transistor.

10. The circuit of claim 8 , further comprising:

a sixteenth resistor connected between the node between the twelfth and thirteenth resistors and ground.

11. The circuit of claim 8 , further comprising:

a first capacitor connected in parallel with the sixth resistor.

12. A driver circuit, comprising:

first and second transistors forming a differential pair and having their sources connected together and their gates connected to a differential input signal;

first and second resistors connected in series between the first transistor and ground and having a first output node between the first and second resistors;

third and fourth resistors connected in series between the second transistor and ground and having a second output node between the third and fourth resistors;

a third transistor having a drain connected to sources of the first and second transistors;

a fourth transistor in series with a first current source and biasing a gate of the third transistor; and

a fifth transistor connected between a power supply and a source of the third transistor.

13. The circuit of claim 12 , further comprising:

a sixth transistor connected between the power supply and a source of the fourth transistor, wherein a gate of the sixth transistor is connected to a gate of the fifth transistor and to a drain of the fourth transistor.

14. The circuit of claim 13 , further comprising:

a seventh transistor and a second current source in series between the power supply and a ground, wherein a gate of the seventh transistor is connected to the gate of the fifth transistor and to the second current source.

15. The circuit of claim 14 , further comprising:

fifth and sixth resistors in parallel with the second and fourth resistors, respectively.

16. The circuit of claim 15 , further comprising:

seventh and eighth transistors connected in series between the fourth resistor and the ground;

eighth and ninth resistors connected in parallel with the fourth resistor and the seventh and eighth transistors;

a comparator comparing a reference voltage with voltage from a node between the seventh and eighth resistors; and

a logic circuit inputting an output of the comparator, and having an output connected to a gate of the ninth transistor to control the ninth transistor based on the output of the comparator.