IP Library Granted Patent US 7,521,288
Granted Patent B2
US 7,521,288 · App. 11/717,953 · Granted Apr 21, 2009

Stacked chip semiconductor device and method for manufacturing the same

Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 7,521,288
App. No.
11/717,953
Granted
Apr 21, 2009
Kind
B2
Abstract

A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip. Thereby, influences of the fillet made of the adhesive are suppressed, allowing miniaturization of the device and improvement in the mass-productivity.

Claims (12)

1. A method for manufacturing a stacked chip semiconductor device, comprising:

flip-chip mounting a first semiconductor chip having electrode pads to a substrate;

injecting an adhesive into a gap between the substrate and the first semiconductor chip so as to form a first adhesive layer of the adhesive with a fringe protruding from an edge of the first semiconductor chip to form a fillet;

bonding a second semiconductor chip on an upper part of the first semiconductor chip via a second adhesive layer;

connecting electrode pads of the second semiconductor chip and the electrode pads of the substrate via wires; and

encapsulating the first semiconductor chip, the second semiconductor chip and the wires with a molded resin, wherein

in the flip-chip mounting, the first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side from which the adhesive is injected in the underfilling.

2. The method according to claim 1 , wherein the second semiconductor chip is mounted substantially at a center of the substrate.

3. The method according to claim 1 , wherein the step of bonding the second semiconductor chip is carried out before the step of injecting the adhesive.

4. The method according to claim 3 , wherein the second semiconductor chip is mounted in the stack-die-bonding so as to be flush with the side of the first semiconductor chip at which the adhesive is injected.

5. The method according to claim 1 , wherein a size of the second semiconductor chip is smaller than that of the first semiconductor chip.

6. The method according to claim 5 , wherein at least one pair of edges on opposite sides of the first semiconductor chip project from corresponding edges of the second semiconductor chip, respectively, and projecting lengths of the first semiconductor chip in a direction of the offset are different from each other.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: PANNOVA SEMIC, LLC
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 037581/0466 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
Priority Claims (1)
JP 2003-192139 · Jul 4, 2003 · national
Continuity (2)
Division 1088104400 · Jun 30, 2004
Related Publication 20070187811A1 · Aug 16, 2007