Method of fabricating a dual-gate structure that prevents cut-through and lowered mobility
View Patent ↗A method of fabricating a dual-gate semiconductor device, including forming a first PMOS transistor on a semiconductor substrate, the first PMOS transistor having a first gate electrode and a first gate insulation layer; and forming a first NMOS transistor on the semiconductor substrate, the first NMOS transistor having a second gate electrode and a second gate insulation layer. The gate insulation layer of the first PMOS transistor is a silicon nitride oxide layer.
1. A method of fabricating a semiconductor comprising:
forming a first region and a second region in a substrate, the first region having p-type conductivity and the second region having n-type conductivity;
forming a silicon oxide layer on the first and second regions;
depositing a first polysilicon layer on an entirety of the silicon oxide layer;
removing part of the first polysilicon layer so that the silicon oxide layer over the second region is exposed and so that a portion of the first polysilicon layer remains over the first region;
forming a silicon nitride layer on the remaining first polysilicon layer;
removing the silicon oxide layer from over the second region using the silicon nitride layer as a mask;
forming a silicon nitride oxide layer on the substrate in the second region using the silicon nitride layer as a mask;
depositing a second polysilicon layer over the first and second regions on the silicon nitride layer and on the silicon nitride oxide layer;
removing part of the second polysilicon layer so that the silicon nitride layer is exposed above the first region and so that a portion of the second polysilicon layer remains over the second region;
removing the silicon nitride layer; and
patterning the silicon oxide layer, the remaining first polysilicon layer, the silicon nitride oxide layer and the remaining second polysilicon layer, to respectively form a first gate insulator and a first gate in the second region, and a second gate insulator and a second gate in the second region.
2. The method of fabricating a semiconductor device of claim 1 , further comprising:
implanting source and drain regions of n-type conductivity adjacent the first gate, to form an NMOS transistor in the first region; and
implanting source and drains regions of p-type conductivity adjacent the second gate, to form a PMOS transistor in the second region.
3. The method of fabricating a semiconductor device of claim 2 , further comprising implanting impurities into the substrate at the first and second regions prior to said forming a silicon oxide layer, to control threshold voltages of the NMOS and PMOS transistors.
4. The method of fabricating a semiconductor device of claim 1 , wherein a thickness of the silicon oxide layer and a thickness of the silicon nitride oxide layer are the same.
5. The method of fabricating a semiconductor device of claim 1 , wherein a thickness of the silicon oxide layer and a thickness of the silicon nitride oxide layer are different.
6. The method of fabricating a semiconductor device of claim 1 , wherein the silicon oxide layer and the silicon nitride oxide layer are 2.5 nm thick.
7. The method of fabricating a semiconductor device of claim 1 , wherein the remaining first polysilicon layer has a 60 degree taper at an edge thereof.
8. The method of fabricating a semiconductor device of claim 1 , further comprising implanting an impurity into the first polysilicon layer prior to said removing the first polysilicon layer.