IP Library Granted Patent US 7,566,662
Granted Patent B2
US 7,566,662 · App. 11/733,316 · Granted Jul 28, 2009

Method of dry cleaning silicon surface prior to forming self-aligned nickel silicide layer

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Quick Facts
Patent No.
US 7,566,662
App. No.
11/733,316
Granted
Jul 28, 2009
Kind
B2
Abstract

Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.

Claims (41)

1. A method of manufacturing a semiconductor device by forming a nickel silicide layer in self alignment, comprising, prior to the deposition of a nickel film over silicon, the steps of:

(a) placing a semiconductor wafer over a wafer stage with which a first chamber is equipped;

(b) dry cleaning a surface of the silicon over a main surface of the semiconductor wafer with a reducing gas supplied via a shower head located above the wafer stage;

(c) heat treating the semiconductor wafer at a first temperature which has utilized a heating temperature of the shower head;

(d) transferring the semiconductor wafer from the first chamber to a second chamber; and

(e) heat treating the semiconductor wafer in the second chamber at a second temperature greater than the first temperature.

2. A method of manufacturing a semiconductor device according to claim 1 , wherein the first temperature is from 100 to 150° C.

3. A method of manufacturing a semiconductor device according to claim 1 , wherein the second temperature is from 150 to 400°C.

4. A method of manufacturing a semiconductor device according to claim 1 , wherein the second temperature is from 165 to 350° C.

5. A method of manufacturing a semiconductor device according to claim 1 , wherein the second temperature is from 180 to 220° C.

6. A method of manufacturing a semiconductor device according to claim 1 , wherein the second temperature is 200° C.

7. A method of manufacturing a semiconductor device according to claim 1 , wherein the semiconductor wafer is vacuum-transferred between the first chamber and the second chamber.

8. A method of manufacturing a semiconductor device according to claim 1 , wherein the silicon is polycrystalline silicon constituting a gate electrode of a field effect transistor or single crystal silicon constituting the semiconductor wafer in which source and drain diffusion regions are formed.

9. A method of manufacturing a semiconductor device by forming a nickel silicide layer in self alignment, comprising, prior to the deposition of a nickel film over silicon, the steps of:

(a) placing a semiconductor wafer over a wafer stage with which a first chamber is equipped;

(b) dry cleaning a surface of the silicon over a main surface of the semiconductor wafer with a reducing gas supplied via a shower head located above the wafer stage; and

(c) heat treating the semiconductor wafer at a first temperature which has utilized the heating temperature of the shower head,

wherein the shower head is maintained at a temperature greater than 180° C.

10. A method of manufacturing a semiconductor device according to claim 9 , wherein the first temperature is from 180 to 220° C.

11. A method of manufacturing a semiconductor device according to claim 9 , wherein the first temperature is 200° C.

12. A method of manufacturing a semiconductor device according to claim 9 , wherein the silicon is polycrystalline silicon constituting a gate electrode of a field effect transistor or single crystal silicon constituting the semiconductor wafer in which source and drain diffusion regions are formed.

13. A method of manufacturing a semiconductor device by forming a nickel silicide layer in self alignment, comprising, prior to the deposition of a nickel film over silicon, the steps of:

(a) placing a semiconductor wafer over a wafer stage with which a first chamber is equipped;

(b) dry cleaning a surface of the silicon over a main surface of the semiconductor wafer with a reducing gas supplied via a shower head located above the wafer stage;

(c) transferring the semiconductor wafer from the first chamber to the second chamber; and

(d) heat treating the semiconductor wafer at a second temperature in the second chamber,

wherein in the step (b), no reducing gas is supplied to the side surface and back surface of the semiconductor wafer.

14. A method of manufacturing a semiconductor device according to claim 13 , wherein the second temperature is from 150 to 400° C.

15. A method of manufacturing a semiconductor device according to claim 13 , wherein the second temperature is from 165 to 350° C.

16. A method of manufacturing a semiconductor device according to claim 13 , wherein the second temperature is from 180 to 220° C.

17. A method of manufacturing a semiconductor device according to claim 13 , wherein the second temperature is 200° C.

18. A method of manufacturing a semiconductor device according to claim 13 , wherein the step (b) comprises a sub-step of:

(b1) holding down, with a sealing, the peripheral portion of the semiconductor wafer placed over the wafer stage.

19. A method of manufacturing a semiconductor device according to claim 13 , wherein the step (b) comprises the sub-steps of:

(b1) adsorbing the semiconductor wafer onto the wafer stage by using an electrostatic chuck; and

(b2) covering the peripheral portion of the semiconductor wafer with a shadow ring without bringing the ring into contact with the semiconductor wafer and supplying an inert gas from the peripheral portion of the wafer stage.

20. A method of manufacturing a semiconductor device according to claim 13 , wherein the step (b) comprises the sub-steps of:

(b1) holding down, with a sealing, the peripheral portion of the semiconductor wafer placed over the wafer stage; and

(b2) supplying an inert gas from the back side of the wafer stage.

21. A method of manufacturing a semiconductor device according to claim 13 , wherein the semiconductor wafer is vacuum-transferred from the first chamber to the second chamber.

22. A method of manufacturing a semiconductor device according to claim 13 , wherein the silicon is polycrystalline silicon constituting a gate electrode of a field effect transistor or single crystal silicon constituting the semiconductor wafer in which source and drain diffusion regions are formed.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER Recorded Jul 30, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025204/0512 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2007
From: FUTASE, TAKUYA; TSUGANE, HIDEAKI; KIMOTO, MITSUO; SUZUKI, HIDENORI
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 019175/0843 →