Semiconductor memory device which controls refresh of a memory array in normal operation
View Patent ↗A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.
1. A semiconductor memory device comprising a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation,
wherein said refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to said dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of said dummy bit when receiving the refresh request.
2. A semiconductor memory device according to claim 1 , wherein when receiving the refresh request, refresh is performed if said dummy bit is 0 and refresh is not performed if said dummy bit is 1.
3. A semiconductor memory device according to claim 1 , wherein a predetermined bit of the row address is redundant in refresh operation and two word lines corresponding to row addresses of which said predetermined bit is 0 and 1 are to be refreshed when receiving the refresh request.
4. A semiconductor memory device according to claim 3 , wherein each row address includes a group of bits for selecting a block among a plurality of blocks into which an entire memory area is divided, and said predetermined bit being redundant is included in said group of bits.
5. A semiconductor memory device according to claim 1 , wherein the entire said refresh counter forms an N-ary counter, and the most significant bit of said refresh counter is assigned to said dummy bit.
6. A semiconductor memory device according to claim 1 , wherein lower m bits of said refresh counter forms an N-ary counter, and the most significant bit of said m bits is assigned to said dummy bit.
7. A semiconductor memory device according to claim 1 , wherein by determining whether or not a predetermined bit not assigned to said refresh counter is redundant according to a value of the row address when receiving the refresh request, two word lines corresponding to the row addresses of which said predetermined bit is 0 and 1 are to be refreshed if said predetermined bit is redundant, and one word line selected from said two word lines in response to said dummy bit is to be refreshed if said predetermined bit is not redundant.
8. A semiconductor memory device according to claim 7 , wherein N of said N-ary counter is set so as to satisfy 2 m−1 <N<2 m .
9. A semiconductor memory device comprising a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation,
wherein said refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, lower m bits of said refresh counter forms an N-ary counter, and the most significant bit of said m bits is assigned to said dummy bit so as to control whether or not refresh is performed in response to a value of said dummy bit when receiving the refresh request.