Squelch detection system for high speed data links
View Patent ↗An apparatus comprising a first comparator circuit, a second comparator circuit, a third comparator circuit, and a difference circuit. The first comparator circuit may be configured to generate a first intermediate current in response to a first input voltage and a second input voltage. The second comparator circuit may be configured to generate a second intermediate current in response to the first input voltage and the second input voltage. The third comparator circuit may be configured to generate an intermediate reference current in response to a first reference voltage and a second reference voltage. The difference circuit may be configured to generate a first compare voltage and a second compare voltage in response to the first intermediate current, the second intermediate current, and the intermediate reference current. The apparatus may indicate a squelch condition when the first compare voltage is greater than the second compare voltage.
1. An apparatus comprising:
a first comparator circuit configured to generate a first intermediate current in response to a first input voltage and a second input voltage;
a second comparator circuit configured to generate a second intermediate current in response to said first input voltage and said second input voltage;
a third comparator circuit configured to generate an intermediate reference current in response to a first reference voltage and a second reference voltage;
a difference circuit configured to generate a first compare voltage and a second compare voltage in response to said first intermediate current, said second intermediate current, and said intermediate reference current, wherein said apparatus indicates a squelch condition when said first compare voltage is greater than said second compare voltage.
2. The apparatus according to claim 1 , wherein said apparatus is implemented in a Universal Serial Bus system.
3. The apparatus according to claim 1 , wherein said first comparator circuit, said second comparator circuit, and said third comparator circuit are implemented as similar difference circuits.
4. The apparatus according to claim 1 , wherein said first comparator and said second comparator each have a first input and a second input, wherein (i) said first input of said first comparator and said second input of said second comparator receive said first input voltage and (ii) said second input of said first comparator and said first input of said second comparator receive said second voltage input.
5. The apparatus according to claim 1 , wherein said difference circuit comprises: a first portion comprising a first transistor and a second transistor connected to said intermediate reference current, wherein said first portion present an intermediate voltage; and a second portion comprising a first and a second current source wherein said second portion is configured to generate a differential output signal comprising said first compare voltage and a second compare voltage.
6. The apparatus according to claim 1 , wherein said apparatus is implemented in a Firewire system.
7. The apparatus according to claim 1 , wherein said apparatus is implemented in a Serial ATA system.
8. The apparatus according to claim 1 , wherein said apparatus is implemented in a high speed data bus system.
9. An apparatus comprising:
means for generating a first intermediate current in response to a first input voltage and a second input voltage;
means for generating a second intermediate current in response to said first input voltage and said second input voltage;
means for generating an intermediate reference current in response to a first reference voltage and a second reference voltage;
means for generating a first compare voltage and a second compare voltage in response to said first intermediate current, said second intermediate current, and said intermediate reference current, wherein said apparatus indicates a squelch condition when said first compare voltage is greater than said second compare voltage.
10. A method for squelch detection on a high speed data bus, comprising the steps of:
(A) generating a first intermediate current in response to a first input voltage and a second input voltage;
(B) generating a second intermediate current in response to said first input voltage and said second input voltage;
(C) generating an intermediate reference current in response to a first reference voltage and a second reference voltage;
(D) generating a first compare voltage and a second compare voltage in response to said first intermediate current, said second intermediate current, and said intermediate reference current, wherein said method indicates a squelch condition when said first compare voltage is greater than said second compare voltage.
11. The method according to claim 10 , wherein said method is implemented in a Universal Serial Bus system.
12. The method according to claim 10 , wherein said method is implemented in a Firewire system.
13. The method according to claim 10 , wherein said method is implemented in a Serial ATA system.
14. The method according to claim 10 , wherein said method is implemented in a high speed data bus system.
15. The method according to claim 10 , wherein steps (A), (B) and (C) are implemented using similar difference circuits.