Apparatus and method for phase lock gain control using unit current sources
View Patent ↗A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for-changing PLL operating conditions, in addition to compensating for variable VCO gain.
1. A method of adjusting a signal frequency in a radio frequency (RF) device, comprising:
selecting an oscillator from a plurality of oscillators, the plurality of oscillators being operatively coupled to a loop filter;
inputting a first signal that is a function of a reference signal;
inputting a second signal that is a function of a signal of the selected oscillator;
comparing the first signal and the second signal;
selectively adding or removing capacitance to an LC circuit that is operatively coupled to the selected oscillator; and
selectively activating a group of a plurality of groups of current sources within a gain cell associated with the selectively added or removed capacitance, the selectively activated group contributing to a charge pump current.
2. The method according to claim 1 , wherein the LC circuit comprises capacitors in a parallel circuit configuration.
3. The method according to claim 2 ,
wherein the capacitors are operatively coupled to switches, each capacitor being operatively coupled to a respective switch, and
wherein the respective switch switches the corresponding capacitor into or out of the LC circuit.
4. The method according to claim 3 , comprising:
digitally controlling the switches.
5. The method according to claim 1 ,
wherein the selected oscillator comprises a first transistor and a second transistor,
wherein an output of the first transistor is operatively coupled to an input of the second transistor, and
wherein an output of the second transistor is operatively coupled to an input of the first transistor.
6. The method according to claim 5 ,
wherein the LC circuit comprises a first diode and a second diode, and
wherein the first diode and the second diode are in a series circuit configuration, and
wherein the first diode and the second diode are operatively coupled between the output of the first transistor and the output of the second transistor.
7. The method according to claim 6 ,
wherein the first diode comprises a first varactor diode, and
wherein the second diode comprises a second varactor diode.
8. The method according to claim 7 , wherein the first diode and the second diode are operatively coupled such that a forward-bias current path of the first diode is opposite in direction to a forward-bias current path of the second diode.
9. The method according to claim 1 , wherein the selected oscillator is part of a phase lock loop (PLL) circuit.
10. The method according to claim 9 , comprising:
selecting the gain cell of a plurality of gain cells, the selected gain cell being associated with the selected oscillator, the selected gain cell contributing to the charge pump current.
11. The method according to claim 9 , wherein the PLL circuit comprises a window comparator.
12. The method according to claim 9 , wherein the PLL circuit comprises a frequency divider, a phase detector, a charge pump, a loop filter and the selected oscillator.
13. The method according to claim 12 ,
wherein the frequency divider is operatively coupled to the phase detector,
wherein the phase detector is operatively coupled to the charge pump,
wherein the charge pump is operatively coupled to the loop filter,
wherein the loop filter is operatively coupled to the selected oscillator, and
wherein the selected oscillator is operatively coupled to the frequency divider.
14. The method according to claim 9 , comprising:
attempting to keep a gain of the PLL circuit flat for variations in switched capacitance.
15. The method according to claim 9 , comprising:
attempting to keep a gain of the PLL circuit flat for variations in gain of the selected oscillator.
16. The method according to claim 9 , comprising:
attempting to keep a gain of the PLL circuit flat for variations in operating conditions of the selected oscillator.
17. The method according to claim 1 , comprising:
adjusting a frequency of the signal of the selected oscillator as a function of the selectively added or removed capacitance.
18. The method according to claim 1 , wherein the selected oscillator is used in a PLL circuit that is used in or with an RF receiver.
19. The method according to claim 18 , wherein the PLL circuit is used to provide a downconversion signal to a mixer of the RF receiver.
20. The method according to claim 18 , wherein the PLL circuit is used to provide an upconversion signal to a mixer of the RF receiver.