Wireless data communications using FIFO for synchronization memory
View Patent ↗A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.
1. A Bluetooth receiver comprising:
a receiver circuit adapted to receive a wireless signal having a frequency of about 2.4 GHz;
a demodulator coupled to the receiver circuit, the demodulator adapted to recover a data signal and a first clock signal from a signal output by the receiver circuit;
a host adapted to generate a second clock signal;
a first-in first-out memory (FIFO) coupled to the demodulator and adapted to to receive the data signal and the first clock signal,
wherein the FIFO is adapted to store the data signal in synchronization with the first clock signal, and wherein the FIFO is coupled to the host to receive the second clock signal.
2. The Bluetooth device of claim 1 , wherein the FIFO is adapted to output an output data signal in synchronization with the second clock signal.
3. The Bluetooth device of claim 2 , wherein the FIFO is adapted to store the data signal and to output the output data signal at substantially the same rate.
4. The Bluetooth device of claim 2 , wherein the host is coupled to the FIFO to receive the output data signal from the FIFO.
5. The Bluetooth device of claim 2 , further comprising a data processing circuit coupled to the FIFO to receive the output data signal.
6. The Bluetooth device of claim 5 , wherein the data processing circuit includes at least one of a forward error correction circuit, a cyclical redundancy check circuit, a de-whitening circuit, a second FIFO, a clock, a microcontroller, and/or a host interface to generate a processed data signal.
7. The Bluetooth device of claim 5 , wherein the host is coupled to the data processing circuit to receive the processed data signal.
8. The Bluetooth device of claim 5 , wherein the FIFO further outputs a full or empty signal to the data processing circuit.
9. The Bluetooth device of claim 1 , wherein the FIFO is adapted to output an output data signal at substantially the same rate at which the data signal is stored in the FIFO.
10. The Bluetooth device of claim 1 , wherein the FIFO is coupled to the host to output an output data signal to the host.
11. The Bluetooth device of claim 1 , wherein the wireless signal is transmitted from a second Bluetooth device.
12. A Bluetooth device system comprising:
a receiver circuit adapted to receive a wireless signal having a frequency of about 2.4 GHz;
a demodulator coupled to the receiver circuit, the demodulator adapted to recover a data signal and at least one clock signal from at least one signal output by the receiver circuit;
a host adapted to generate a read signal;
and a first-in first-out memory coupled to the demodulator and adapted to receive the data signal and the at least one clock signal, wherein the first-in first-out memory is adapted to store the data signal in response to the at lest one clock signal, and wherein the first-in first-out memory is coupled to the host to receive the read signal;
wherein the host is adapted to read the data signal from the first-in first-out memory without synchronizing a clock to the at least one clock signal.
13. The Bluetooth device system of the claim 12 wherein the read signal is synchronized with a host clock signal.
14. The Bluetooth device system of claim 12 wherein the host is adapted to operate at a higher speed than the at least one clock signal.
15. The Bluetooth device system of claim 12 wherein the host is adapted to read the data signal from the first-in first-out memory in bursts.
16. The Bluetooth device system of claim 12 wherein the first-in first-out memory is sized in accordance with a variation between a rate at which the first-in first-out memory is written and a rate at which the first-in first-out memory is read.
17. The Bluetooth device system of claim 12 wherein the first-in first-out memory is sized in accordance with a length of data transmitted.
18. The Bluetooth device system of claim 12 wherein the first-in first-out memory is sized in accordance with a product of a length of data transmitted and a variation between a rate at which the first-in first-out memory is written and a rate at which the first-in first-out memory is read.
19. The Bluetooth device of claim 12 , wherein the wireless signal is transmitted from a second Bluetooth device.