Method and system for performing built-in-self-test routines using an accumulator to store fault information
View Patent ↗A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.
1. A method of testing integrated circuits having built-in self-test circuitry and built-in self-repair circuitry, said method comprising the steps of:
establishing a selectively variable stress condition in an integrated circuit die;
performing a built-in self-test operation to detect faults in selectively designated memory space, including redundant memory, of said integrated circuit die;
generating fault information relating to any faults detected by the built-in self-test operation;
cumulatively storing the fault information;
iteratively repeating the stress condition establishing step, the built-in self-test operation performance step, the fault information generation step, and the fault information cumulative storage step; and
performing a built-in self-repair operation to reconfigure any faulty portions of the integrated circuit die as indicated by the cumulatively stored fault information from all iterations of the stress condition establishing step, the built-in self-test operation performance step, the fault information generation step, and the fault information cumulative storage step following completion of the last iteration.
2. The method as recited in claim 1 , further comprises the steps of:
providing a storage area for use in cumulatively storing the fault information; and
resetting the storage area, prior to storage of fault information associated with initial performance of the built-in self-test operation.
3. The method as recited in claim 1 , further comprises in each testing iteration the steps of:
defining a fault count based upon the cumulatively stored fault information; and
comparing the fault count to a repair count.
4. The method as recited in claim 3 , further comprises in each testing iteration the step of:
rejecting the integrated circuit die if the fault count exceeds the repair count, as indicated by the comparison operation.
5. The method as recited in claim 3 , wherein the fault count relating to faulty memory locations, and the repair count relating to redundant memory locations.
6. The method as recited in claim 1 , wherein the fault information being representative of memory address locations.
7. The method as recited in claim 6 , further comprises the step of:
performing a built-in self-repair operation to remap the memory address locations represented by the cumulatively stored fault information to redundant memory address locations.
8. The method as recited in claim 1 , wherein the step of performing a built-in self-test operation further comprises the steps of:
generating a test pattern using the built-in self-test circuitry; and
exercising the at least a portion of the integrated circuit die with the test pattern.
9. The method as recited in claim 1 , wherein the step of establishing a selectively variable stress condition in the integrated circuit die further comprises the step of:
selectively setting at least one of an environmental factor and an operational factor in relation to the integrated circuit die.
10. The method as recited in claim 1 , wherein the step of establishing a selectively variable stress condition in the integrated circuit die further comprises the step of:
selectively setting at least one of a voltage condition and a temperature condition of the integrated circuit die.
11. The method as recited in claim 1 , wherein the at least a portion of the integrated circuit die comprises a memory.
12. The method as recited in claim 11 , wherein the memory includes a dynamic random access memory.
13. The method as recited in claim 11 , wherein the memory includes a static random access memory.
14. A method of testing integrated circuits having built-in self-test circuitry and built-in self-repair circuitry, said method comprising the steps of:
iteratively performing a test routine; each iteration of the test routine comprising the steps of:
establishing a selectively variable stress condition in an integrated circuit die,
performing a built-in self-test operation to detect faults in selectively
designated memory space, including redundant memory, of said integrated circuit die,
generating fault information relating to any faults detected by the built-in self-test operation;
cumulatively storing the fault information; and
performing a built-in self-repair operation to reconfigure any faulty portions of the integrated circuit die as indicated by the cumulatively stored fault information from all iterations of the test routine, following completion of the last test routine iteration.
15. The method as recited in claim 14 , further comprises the steps of:
providing a storage area for use in cumulatively storing the generated fault information; and
resetting the storage area, prior to storage of fault information associated with a first iteration of the test routine.
16. The method as recited in claim 14 , wherein each iteration of the test routine further comprises the steps of:
defining a fault count based upon the cumulatively stored fault information; and
comparing the fault count to a repair count.
17. The method as recited in claim 16 , wherein each iteration of the test routine further comprises the step of:
rejecting the integrated circuit die if the fault count exceeds the repair count, as indicated by the comparison operation.
18. The method as recited in claim 16 , wherein the fault count relating to faulty memory locations, and the repair count relating to redundant memory locations.
19. The method as recited in claim 14 , wherein the fault information being representative of memory address locations.
20. The method as recited in claim 19 , wherein the step of performing a built-in self-repair operation further comprises the step of:
remapping the memory address locations represented by the cumulatively stored fault information to redundant memory address locations.
21. The method as recited in claim 14 , wherein the step of performing a built-in self-test operation further comprises the steps of:
generating a test pattern using the built-in self-test circuitry; and
exercising the at least a portion of the integrated circuit die with the test pattern.
22. The method as recited in claim 14 , wherein the step of establishing a selectively variable stress condition in the integrated circuit die further comprises the step of:
selectively setting at least one of an environmental factor and an operational factor in relation to the integrated circuit die.
23. The method as recited in claim 14 , wherein the step of establishing a selectively variable stress condition in the integrated circuit die further comprises the step of:
selectively setting at least one of a voltage condition and a temperature condition of the integrated circuit die.
24. The method as recited in claim 14 , wherein the at least a portion of the integrated circuit die comprises a memory.
25. The method as recited in claim 24 , wherein the memory includes a dynamic random access memory.
26. The method as recited in claim 24 , wherein the memory includes a static random access memory.