IP Library Patent Application 11861089
Patent Application
App. No. 11/861,089

FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

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Quick Facts
Patent No.
US None
App. No.
11/861,089
Abstract

To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Claims (8)

1 . A fabrication method of a semiconductor integrated circuit device, comprising the steps of:

(a) providing a semiconductor wafer having a plurality of chip regions each having a semiconductor integrated circuit and a plurality of electrodes electrically connected to said semiconductor integrated circuit over a main surface of said semiconductor wafer;

(b) providing a probe card having a sheet member with a plurality of contact terminals to be brought into contact with the electrodes of said semiconductor wafer, tip portions of said contact terminals being disposed so as to be opposite to said main surface of said semiconductor wafer;

(c) subjecting said semiconductor wafer to ashing treatment, thereby to eliminate a dust from said main surface of said semiconductor wafer; and

(d) after the step (c), performing electrical testing of said semiconductor integrated circuit by bringing said tip portions of said contact terminals into contact with said electrodes of said semiconductor wafer by a pressing mechanism for pressing a rear surface side of said sheet member.

2 . A fabrication method according to claim 1 , wherein said ashing treatment includes a step of supplying oxygen plasma to said main surface of said semiconductor wafer.

3 . A fabrication method according to claim 2 , wherein said probe card further includes a supporting base disposed on said rear surface side of said sheet member and a wiring substrate electrically connected to said contact terminals of said sheet member, and wherein said pressing mechanism provides pressing force to said supporting base to contact said contact terminals with said electrodes of said semiconductor wafer.

4 . A fabrication method according to claim 3 , wherein said sheet member includes a deformable thin film sheet.

Assignments (1)
MERGER Recorded Jul 23, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024736/0381 →