IP Library Granted Patent US 7,949,012
Granted Patent B2
US 7,949,012 · App. 11/861,700 · Granted May 24, 2011

High-speed uplink packet access (HSUPA) cipher multiplexing engine

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Quick Facts
Patent No.
US 7,949,012
App. No.
11/861,700
Granted
May 24, 2011
Kind
B2
Abstract

A combined data packing, cipher and multiplexing engine operable to support high speed uplink packet access (HS-UPA) within user equipment (UE) is provided. This combined cipher multiplexing engine includes a master port, a radio link control (RLC) data packer, and a cipher multiplexing processing module. The master port couples to an advanced microprocessor bus architecture (AMBA) high speed buss (AHB) on which control information for the combined cipher and multiplexing engine is provided. The RLC couples to the master port and receives RLC service data units (SDUs) from the AHB. Then the RLC data packer may concatenate or segment RLC SDUs into RLC packet data units (PDUs) which are stored for use by a cipher multiplexing processing module. The cipher multiplexing processing module retrieves the RLC PDU from the RLC PDU buffer and ciphers to produce ciphered data, if cipher is enabled and multiplexes the ciphered/non-ciphered data together with the RLC header, MAC-es header, MAC-e header and enters the multiplexed results to a hybrid automatic repeat request (HARQ) buffer. A protocol stack executed within the UE activates and provides an array on the formation of the RLC PDU, RLC header information to the combined cipher and multiplexing engine for RLC PDU ciphering and medium access control (MAC) multiplexing of the enhanced data transport channel (E-DCH).

Claims (79)

1. A combined data packing, cipher and multiplexing engine operable to support high speed uplink packet access (HS-UPA) within user equipment (UE), comprising:

a master port coupled to an advanced microprocessor bus architecture (AMBA) high speed bus (AHB) on which control information for the combined data packing, cipher and multiplexing engine received;

a radio link control (RLC) data packer coupled to the master port, the RLC data packer operable to:

receive RLC service data units (SDUs) from the AHB via the master port;

concatenate or segment RLC SDUs into RLC packet data units (PDUs); and

store RLC PDUs to a RLC PDU buffer; and

a cipher/multiplexing processing module operable to:

retrieve the RLC PDU from the RLC PDU buffer;

cipher the RLC PDU to produce ciphered data, when cipher enabled; and

enter the ciphered data to a Hybrid Automatic Repeat reQuest (HARQ) buffer; and

wherein a protocol stack executed within the UE activates and provides an array on the formation of the RLC PDU, RLC header information to the combined data packing, cipher and multiplexing engine for RLC PDU ciphering and Medium Access Control (MAC) multiplexing of an enhanced dedicated transport channel (E-DCH).

2. The combined data packing, cipher and multiplexing engine of claim 1 , wherein:

RLC PDU's are stored within a retransmission buffer; and

deleted or retransmitted based on a status report sent from a peer RLC entity.

3. The combined data packing, cipher and multiplexing engine of claim 1 , wherein each RLC PDU comprises:

a destination address of the RLC PDU (i.e. memory address that stores output of the datapacker; and

a source address of an array of data structure that describes the RLC SDUs to be packed.

4. The combined cipher and multiplexing engine of claim 1 , wherein the HARQ buffer is operable to store multiple transport blocks for multiple HARQ processor and provide resynchronization to a transmit engine.

5. The combined data packing, cipher and multiplexing engine of claim 1 , wherein the RLC datapacker outputs the RLC PDUs to a system memory available through the AHB.

6. The combined data packing, cipher and multiplexing engine of claim 1 , wherein the RLC datapacker outputs the RLC PDUs directly to the internal memory of the cipher/multiplexing processing module.

7. The combined data packing, cipher and multiplexing engine of claim 1 , wherein RLC PDUs are processed by a medium access control (MAC) layer to produce transport blocks for E-DCH transmission.

8. A method operable produce transport blocks for enhanced dedicated channel (E-DCH) transmission within high speed uplink packet access (HS-UPA) capable user equipment (UE), comprising:

generating an array directed to a formation of a radio link control (RLC) header, RLC packet data units (PDUs), and medium access control (MAC)-e/es multiplexing, wherein the array is generated by a protocol stack within the UE;

providing the array to a combined data packing, cipher and multiplexing engine, the combined data packing, cipher and multiplexing engine comprising:

a RLC datapacker; and

a cipher/multiplexing processing module;

generating, with the RLC datapacker, RLC PDUs from RLC service data units (SDUs) based on the array;

activating the cipher/multiplexing processing module;

ciphering with the cipher/multiplexing processing module, when directed by the array, the RLC PDUs;

producing, with the cipher/multiplexing processing module, MAC-d PDUs from the RLC PDUs;

multiplexing, with the cipher/multiplexing processing module, MAC-d PDUs from a MAC-d flow to produce a MAC-es PDUs;

multiplexing, with the cipher/multiplexing processing module, MAC-es PDUs from diverse MAC-d flows to produce a MAC-e PDUs; and

producing transport blocks for enhanced dedicated transport channel (E-DCH) transmission from the MAC-e PDUs.

9. The combined data packing, cipher and multiplexing engine of claim 8 , wherein the MAC layer is operable to:

perform a first stage multiplexing operation to produce a MAC-es PDU, the first stage multiplexing operation comprising:

accepting multiple MAC-d PDUs from a MAC-d flow;

multiplex the MAC-d PDUs; and

add a header comprising a transmit sequence number; and

perform a second stage multiplexing operation to produce a MAC-e PDU, the second stage multiplexing operation comprising:

accepting multiple MAC-es PDUs from different MAC-d flow;

multiplex the MAC-es PDUs; and

add a MAC-es header.

10. The method of claim 8 , wherein the multiplexing MAC-d PDUs from a MAC-d flow to produce a MAC-es PDUs comprises:

accepting multiple MAC-d PDUs from a single MAC-d flow;

multiplexing the MAC-d PDUs; and

adding a header comprising a transmit sequence number.

11. The method of claim 8 , wherein the multiplexing MAC-es PDUs from diverse MAC-d flows to produce a MAC-e PDUs comprises:

accepting multiple MAC-es PDUs from different MAC-d flow;

multiplexing the MAC-es PDUs; and

adding a MAC-es header.

12. The method of claim 8 , wherein the combined data packing, cipher and multiplexing engine couples to an advanced microprocessor bus architecture (AMBA) high speed bus (AHB) from which control information for the combined cipher and multiplexing engine and RLC SDUs are received.

13. The method of claim 8 , further comprising:

entering the ciphered RLC PDUs to a Hybrid Automatic Repeat reQuest (HARQ) buffer.

14. The method of claim 8 , wherein the RLC datapacker:

concatenates or segments RLC SDUs into RLC PDUs; and

store RLC PDUs to a RLC PDU buffer.

15. The method of claim 8 , wherein the RLC datapacker activates the cipher/multiplexing processing module after producing the RLC PDUs.

16. The method of claim 8 , wherein each RLC PDU comprises:

a destination address of the RLC PDU (i.e. memory address that stores output of the datapacker; and

a source address of an array of data structure that describes the RLC SDUs to be packed.

17. The method of claim 8 , wherein the RLC datapacker outputs the RLC PDUs to a system memory available through the AHB.

18. The method of claim 8 , wherein the RLC datapacker outputs the RLC PDUs directly to the cipher/multiplexing processing module.

19. The method of claim 8 , wherein the MAC layer is operable to:

perform the multiplexing operation to produce a MAC-es PDU; and

perform the multiplexing operation to produce a MAC-e PDU.

20. The method of claim 8 , wherein the UE operates according to the 3 rd Generation Partnership Agreement (3GPP).

21. A method operable produce transport blocks for enhanced dedicated channel (E-DCH) transmission within high speed uplink packet access (HS-UPA) capable user equipment (UE), comprising:

generating an array directed to a formation of a radio link control (RLC) header, RLC packet data units (PDUs), and medium access control (MAC)-e/es multiplexing, wherein the array is generated by a protocol stack within the UE;

providing the array to a combined data packing, cipher and multiplexing engine, the combined data packing, cipher and multiplexing engine comprising:

a RLC datapacker; and

a cipher/multiplexing processing module;

generating, with the RLC datapacker, RLC PDUs from RLC service data units (SDUs) based on the array;

activating the cipher/multiplexing processing module;

ciphering with the cipher/multiplexing processing module, when cipher enabled, the RLC PDUs;

producing, with the cipher/multiplexing processing module, MAC-d PDUs from the RLC PDUs, wherein the RLC PDUs comprise ciphered RLC PDUs and non-ciphered RLC PDUs;

multiplexing, with the cipher/multiplexing processing module, MAC-d PDUs from a MAC-d flow to produce a MAC-es PDUs;

multiplexing, with the cipher/multiplexing processing module, MAC-es PDUs from diverse MAC-d flows to produce a MAC-e PDUs; and

producing transport blocks for enhanced dedicated transport channel (E-DCH) transmission from the MAC-e PDUs.

22. The method of claim 21 , wherein the cipher/multiplexing processing module is performs data moving and/or copier functions when not cipher enabled.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059721/0014 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL NORTHERN RESEARCH, LLC
Reel/Frame 044886/0331 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2007
From: CHANG, LI FUNG; PREEZ, ANDREW DU
To: BROADCOM CORPORATION
Reel/Frame 020030/0510 →