Memory array of pairs of nonvolatile memory cells using Fowler-Nordheim programming and erasing
View Patent ↗A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.
1. A system comprising:
a program component configured to program one or more non-volatile memory (NVM) cells of an array of pairs of NVM cells using Fowler-Nordhiem (FN) tunneling;
an erase component configured to erase the one or more NVM cells of the array of pairs of NVM cells using FN tunneling; and
a read component configured to read the one or more NVM cells of the array of pairs of NVM cells, wherein the program component is configured to:
apply one or more prohibitive electric fields to prevent charge from being stored in one or more NVM cells of the array of pairs of NVM cells;
apply one or more FN electric fields to cause charge to be stored in one or more other NVM cells of the array of pairs of NVM cells;
remove the one or more FN electric fields; and
remove the one or more prohibitive electric fields.
2. The system of claim 1 , wherein the program component is configured to apply the one or more prohibitive electric fields between a first/second word line and a first/second bit line of the array of pairs of NVM cells.
3. The system of claim 2 , wherein the program component is configured to apply the one or more FN electric fields between the second/first word line and the second/first bit line of the array of pairs of NVM cells.
4. The system of claim 3 , wherein the program component is configured to remove the one or more FN electric fields between the second/first word line and the second/first bit line of the array of pairs of NVM cells.
5. The system of claim 4 , wherein the program component is configured to remove the one or more prohibitive electric fields between the first/second word line and the first/second bit line of the array of pairs of NVM cells.
6. The system of claim 1 , wherein the erase component is configured to:
apply one or more prohibitive electric fields to prevent charge from being removed from one or more NVM cells of the array of pairs of NVM cells;
apply one or more FN electric fields to cause charge to be removed from one or more other NVM cells of the array of pairs of NVM cells;
remove the one or more FN electric fields; and
remove the one or more prohibitive electric fields.
7. The system of claim 1 , wherein the read component is configured to:
apply one or more first electric fields to one or more NVM cells of the array of pairs of NVM cells;
apply one or more second electric fields to one or more other NVM cells of the array of pairs of NVM cells to cause the one or more other NVM cells to exhibit select transistor behavior;
sense whether the one or more NVM cells is conductive;
remove the one or more second electric fields; and
remove the one or more first electric fields.
8. A system comprising:
a program component configured to program one or more non-volatile memory (NVM) cells of an array of pairs of NVM cells using Fowler-Nordhiem (FN) tunneling;
an erase component configured to erase the one or more NVM cells of the array of pairs of NVM cells using FN tunneling; and
a read component configured to read the one or more NVM cells of the array of pairs of NVM cells, wherein the erase component is configured to:
apply one or more prohibitive electric fields to prevent charge from being removed from one or more NVM cells of the array of pairs of NVM cells;
apply one or more FN electric fields to cause charge to be removed from one or more other NVM cells of the array of pairs of NVM cells;
remove the one or more FN electric fields; and
remove the one or more prohibitive electric fields.
9. The system of claim 8 , wherein the erase component is configured to apply the one or more prohibitive electric fields between one or more word and bit lines and a substrate of the array of pairs of NVM cells.
10. The system of claim 9 , wherein the erase component is configured to apply the one or more FN electric fields between the substrate of the array of pairs of NVM cells and one or more other word and bit lines of the array of pairs of NVM cells.
11. The system of claim 10 , wherein the erase component is configured to remove the one or more FN electric fields between the substrate of the array of pairs of NVM cells and the one or more other word and bit lines of the array of pairs of NVM cells.
12. The system of claim 11 , wherein the erase component is configured to remove the one or more prohibitive electric fields between the one or more word and bit lines and the substrate of the array of pairs of NVM cells.
13. The system of claim 8 , wherein the read component is configured to:
apply one or more first electric fields to one or more NVM cells of the array of pairs of NVM cells;
apply one or more second electric fields to one or more other NVM cells of the array of pairs of NVM cells to cause the one or more other NVM cells to exhibit select transistor behavior;
sense whether the one or more NVM cells is conductive;
remove the one or more second electric fields; and
remove the one or more first electric fields.
14. A system comprising:
a program component configured to program one or more non-volatile memory (NVM) cells of an array of pairs of NVM cells using Fowler-Nordhiem (FN) tunneling;
an erase component configured to erase the one or more NVM cells of the array of pairs of NVM cells using FN tunneling; and
a read component configured to read the one or more NVM cells of the array of pairs of NVM cells, wherein the read component is configured to:
apply one or more first electric fields to one or more NVM cells of the array of pairs of NVM cells;
apply one or more second electric fields to one or more other NVM cells of the array of pairs of NVM cells to cause the one or more other NVM cells to exhibit select transistor behavior;
sense whether the one or more NVM cells is conductive;
remove the one or more second electric fields; and
remove the one or more first electric fields.
15. The system of claim 14 , wherein the read component is configured to apply the one or more first electric fields between a first/second word line and a first/second bit line of the array, of pairs of NVM memory cells.
16. The system of claim 15 , wherein the read component is configured to apply the one or more second electric fields between the second/first word line and the second/first bit line of the array of pairs of NVM memory cells.
17. The system of claim 16 , wherein the read component is configured to sense whether the one or more memory cells is conductive by measuring current or voltage on at least one bit line of the array of pairs of NVM cells.
18. The system of claim 17 , wherein the read component is configured to:
apply one or more prohibitive electric fields to create an isolation region that prevents charge transfer between other regions.
19. The system of claim 18 , wherein the read component is configured to apply the one or more prohibitive electric fields between bit lines of the array of pairs of NVM cells.
20. The system of claim 14 , wherein the program component is configured to:
apply one or more prohibitive electric fields to prevent charge from being stored in one or more NVM cells of the array of pairs of NVM cells;
apply one or more FN electric fields to cause charge to be stored in one or more other NVM cells of the array of pairs of NVM cells;
remove the one or more FN electric fields; and
remove the one or more prohibitive electric fields.