Granted Patent B2

US 7,453,724 · App. 11/931,992 · Granted Nov 18, 2008

Abstract

Claims (66)

1. A method for programming a group of non-volatile memory cells in an array of non-volatile memory cells, comprising:

receiving a programming window that identifies a plurality of memory cells in the array of non-volatile memory cells, where the programming window identifies fewer than one half of a total number of non-volatile memory cells in a row of memory cells in the array or more than one half of the total number of non-volatile memory cells in the row of memory cells in the array;

identifying a group of non-volatile memory cells to be programmed from the plurality of memory cells in the programming window;

programming the group of non-volatile memory cells;

determining a programming state for each memory cell in the group of non-volatile memory cells;

storing, in a buffer, the programming state for each memory cell in the group of non-volatile memory cells;

identifying non-programmed memory cells in the group of non-volatile memory cells based on the programming state for each memory cell in the group of non-volatile memory cells stored in the buffer; and

reprogramming the non-programmed memory cells.

2. The method of claim 1 , wherein programming the group of non-volatile memory cells comprises applying programming voltage pulses to the group of non-volatile memory cells.

3. The method of claim 2 , wherein determining the programming state for each of the group of non-volatile memory cells comprises sensing a threshold voltage in each of the group of non-volatile memory cells, where memory cells having a threshold voltage lower than a reference threshold voltage are non-programmed and memory cells having a threshold voltage greater than or equal to the reference threshold voltage are programmed.

4. The method of claim 1 , further comprising:

writing, to the buffer, a value indicative of the programmed state for each memory cell in the group of non-volatile memory cells.

5. The method of claim 1 , wherein determining the programming state of each of the group of non-volatile memory cells comprises:

verifying the programming state of each of the group of non-volatile memory cells.

6. The method of claim 1 , wherein the determining the programming state of each of the group of non-volatile memory cells comprises simultaneously verifying the programming state for each of up to 2,048 memory cells.

7. The method of claim 1 , wherein the array of non-volatile memory cells include SONOS (silicon-oxide-nitride-oxide-silicon) type NOR memory cells.

8. The method of claim 1 , where each memory cell comprises a substrate, a control gate, a charge storage element, a source region and a drain region, and wherein the charge storage element comprises a dielectric charge storage element configured to store at least two independent charges for each memory cell.

9. The method of claim 8 , wherein programming the group of non-volatile memory cells comprises:

applying a first voltage to a control gate of each of the group of non-volatile memory cells; and

applying a second voltage to a drain region of each of the group of non-volatile memory cells.

10. The method of claim 9 , where determining the programming state for each of the group of non-volatile memory cells comprises:

applying a third voltage to the control gate of each of the group of non-volatile memory cells; and

monitoring a threshold voltage in each memory cell in the group of non-volatile memory cells.

11. The method of claim 10 , wherein the third voltage is different from the first voltage.

12. A device, comprising:

an array of non-volatile memory cells;

a state control component for receiving a programming window that identifies a plurality of memory cells in the array of non-volatile memory cells, where the programming window identifies fewer than one half of a total number of non-volatile memory cells in a row of memory cells in the array or more than one half of the total number of non-volatile memory cells in the row of memory cells in the array,

where the state control component identifies a group of non-volatile memory cells to be programmed from the plurality of memory cells in the programming window,

where the state control component is configured to program the group of non-volatile memory cells in the array of non-volatile memory cells;

sense amplifier circuitry to determine a programming state of each of the group of non-volatile memory cells; and

a buffer,

wherein the sense amplifier circuitry is further configured to:

store, in the buffer, the programming state for each memory cell in the group of non-volatile memory cells, and

identify non-programmed memory cells in the group of non-volatile memory cells based on the programming states stored in the buffer, and

wherein the state control component is further configured to reprogram the non-programmed memory cells.

13. The device of claim 12 , wherein the array of non-volatile memory cells comprise:

a plurality of bit lines each connected to source or drain regions of a plurality of the non-volatile memory cells; and

a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of a plurality of the non-volatile memory cells,

wherein the group of non-volatile memory cells corresponds to the non-volatile memory cells along a selected word line.

14. The device of claim 12 , comprising:

a voltage supply component configured to generate at least one programming voltage for programming the group of non-volatile memory cells and a verifying voltage for identifying the non-programmed memory cells in the group of non-volatile memory cells,

wherein the at least one programming voltage and the verifying voltage comprise different voltages.

15. The device of claim 14 , where the state control component is further configured to:

apply a first programming voltage to a control gate of each non-volatile memory cell in the group of non-volatile memory cells; and

apply a second programming voltage to a drain region of each non-volatile memory cell in the group of non-volatile memory cells.

16. The device of claim 14 , where the sense amplifier circuitry is further configured to:

apply the verifying voltage to the control gate of each non-volatile memory cell in the group of non-volatile memory cells; and

compare a threshold voltage in each memory cell in the group of non-volatile memory cells to a threshold voltage of at least one reference memory cell.

17. The device of claim 12 , where each non-volatile memory cell in the array of non-volatile memory cells comprises:

a substrate;

a control gate;

a charge storage element;

a source region; and

a drain region,

wherein the charge storage element comprises a dielectric charge storage element configured to store at least two independent charges for each non-volatile memory cell.

18. A method, comprising:

receiving a programming window that identifies a plurality of memory cells in the array of non-volatile memory cells, where the programming window identifies fewer than one half of a total number of non-volatile memory cells in a row of memory cells in the array or more than one half of the total number of non-volatile memory cells in the row of memory cells in the array;

identifying a group of non-volatile memory cells in an array of non-volatile memory cells;

performing a programming operation on the group of non-volatile memory cells;

writing, to a buffer, values corresponding to programming states for each non-volatile memory cell in the group of non-volatile memory cells;

identifying non-programmed memory cells based on the programming states stored in the buffer; and

performing a second programming operation on the non-programmed memory cells.

19. The method of claim 18 , comprising:

writing values corresponding to the programming states for each of the non-programmed memory cells, following performing the second programming operation, in the buffer;

identifying remaining non-programmed memory cells based on the programming states stored in the buffer; and

performing a third programming operation on the remaining non-programmed memory cells.

Assignments (8)