Packet classification device for storing groups of rules
View Patent ↗A packet classification device includes a CAM device, an SRAM device, and a control circuit that controls and coordinates the operations of the CAM and SRAM devices. For some embodiments, a first CAM block stores unique entries for each packet header field, a RAM block coupled to the first CAM block stores field labels for the unique packet header fields, a second CAM block stores group labels consisting of unique combinations of concatenated field labels, and a second RAM block coupled to the second CAM block stores a group identification (ID) for each group label, wherein each group ID identifies a corresponding one of the groups of rules.
1. A packet classification device for storing a number of groups of rules associated with one or more access control lists (ACLs), wherein each rule includes a plurality of packet header fields and an action field, the packet classification device comprising:
a first content addressable memory (CAM) block configured to store only unique entries for each packet header field;
a first random access memory (RAM) block coupled to the first CAM block and configured to store field labels for the unique packet header field entries stored in the first CAM block, wherein each field label indicates which groups of rules contain the corresponding unique field entry;
a second CAM block configured to store a plurality of group labels, wherein each group label consists of a unique combination of concatenated field labels; and
a second RAM block coupled to the second CAM block and configured to store a group identification (ID) for each group label, wherein each group ID identifies a corresponding one of the groups of rules associated with one or more of the ACLs and stored in the device, wherein each rule includes the packet header fields and the action field.
2. The packet classification device of claim 1 , wherein the packet header fields comprise a source address field and a destination address field.
3. The packet classification device of claim 1 , further including a control circuit coupled to the CAM blocks and to the RAM blocks, the control circuit comprising:
control logic having an input to receive a packet header including a plurality of field values and having an output to provide an action code;
a packet header register coupled to the control logic and configured to store the packet header field values; and
a result register coupled to the control logic and configured to store field labels output from the first RAM block.
4. The packet classification device of claim 3 , wherein:
during first compare operations, the control circuit provides each packet header field value as a separate first search key to the first CAM block for comparison with the unique field entries stored therein, and in response thereto the first RAM block outputs the field labels corresponding to the matching field entries; and
during second compare operations, the control circuit concatenates the field labels output from the first RAM block to form a second search key and provides the second search key to the second CAM block for comparison with the group labels stored therein, and in response thereto the second RAM block outputs the group ID corresponding to the matching group label.
5. The packet classification device of claim 1 , wherein the first CAM block comprises a plurality of independently and simultaneously searchable CAM arrays, wherein each of the CAM arrays is assigned to store the unique entries for a corresponding one of the packet header fields.
6. The packet classification device of claim 5 , wherein:
a first of the CAM arrays is assigned to store source address entries and its corresponding RAM block is assigned to store source address labels; and
a second of the CAM arrays is assigned to store destination address entries and its corresponding RAM block is assigned to store destination address labels.
7. The packet classification device of claim 5 , wherein the first CAM block comprises a plurality of rows of CAM cells divided into a number of segments, wherein the segments within each row are assigned to store the unique entries of different packet header fields.
8. The packet classification device of claim 7 , wherein:
a first of the CAM arrays includes a first segment to store source address entries for a first ACL and includes a second segment to store destination address entries for a second ACL; and
a second of the CAM arrays includes a first segment to store destination address entries for the second ACL and includes a second segment to store source address entries for the first ACL.
9. The packet classification device of claim 1 , wherein each field label stored in the first RAM block comprises an offset value indicating which individual rule the corresponding unique field entry belongs to.
10. The packet classification device of claim 1 , wherein each CAM block comprises a plurality of rows of ternary CAM cells.
11. A packet classification device for storing a number of groups of rules associated with one or more access control lists (ACLs), wherein each rule includes a source address entry and a destination address entry, the packet classification device comprising:
a first content addressable memory (CAM) block configured to store only unique source and destination address entries;
a first random access memory (RAM) block coupled to the first CAM block and configured to store a source address label for each unique source address entry and a destination address label for each unique destination address entry, wherein the address labels indicate which groups of rules contain the corresponding unique address entries;
a second CAM block configured to store a plurality of group labels, wherein each group label comprises a unique concatenation of the source and destination address labels;
a second RAM block coupled to the second CAM block and configured to store a group identification (ID) for each group label, wherein each group ID identifies a corresponding one of the groups of rules associated with one or more of the ACLs and stored in the device, wherein each rule includes the source address entry and the destination address entry; and
a control circuit having an input to receive a packet header containing a source address value and a destination address value.
12. The packet classification device of claim 11 , wherein the control circuit is configured to provide the source and destination address values as first search keys to the first CAM block during first compare operations, to concatenate the source and destination address labels output from the first RAM block in response to match conditions in the first compare operations to generate a second search key, and to provide the second search key to the second CAM block during a second compare operation to determine whether the second search key matches any of the group labels.
13. The packet classification device of claim 12 , wherein the control circuit comprises:
control logic having an input to receive a packet header including a plurality of field values and having an output to provide an action code;
a packet header register coupled to the control logic and configured to store the packet header field values; and
a result register coupled to the control logic and configured to store field labels output from the first RAM block.