Combined processor access and built in self test in hierarchical memory systems
View Patent ↗A hierarchical memory includes a plurality of memory blocks, a common access bus coupled to the plurality of memory blocks, and a host bus interface coupled to the common access bus and configured to provide communication between an external host and the plurality of memory blocks over the common access bus. The memory further includes a Built-In Self Test (BIST) module coupled to the common access bus and configured to communicate with the plurality of memory blocks over the common access bus, and a test access interface coupled to the BIST main module and configured to receive test instructions and test data, to provide the test data to the BIST main module, and to configure the BIST main module in response to the test instructions. BIST operations are carried out in the memory blocks in response to BIST control signals and test data transmitted by the BIST module over the common access bus.
1. A hierarchical memory, comprising:
a plurality of memory blocks;
a common access bus coupled to the plurality of memory blocks;
a host bus interface coupled to the common access bus and configured to provide communication between an external host and each of the plurality of memory blocks over the common access bus;
a Built-In Self Test (BIST) main module coupled to the common access bus and configured to communicate with each of the plurality of memory blocks over the common access bus; and
a test access interface coupled to the BIST main module and configured to:
receive test instructions and test data;
provide the test data to the BIST main module; and
configure the BIST main module in response to the test instructions.
2. The hierarchical memory of claim 1 , further comprising:
a plurality of BIST slave modules in respective ones of the memory blocks, wherein each of the BIST slave modules is configured to communicate over the common access bus with the BIST main module and to carry out BIST functions in its associated memory block in response to test data and configuration instructions provided by the BIST main module.
3. The hierarchical memory of claim 2 , wherein the BIST main module is configured to communicate with the BIST slave modules using a control signal interface comprising a write enable signal, a read enable signal, and a read acknowledge signal.
4. The hierarchical memory of claim 2 , wherein the BIST main module is further configured to communicate with the BIST slave modules using a readback error signal that indicates a readback error in a memory block that is selected to return readback data.
5. The hierarchical memory of claim 4 , wherein the BIST slave modules are configured to transmit the readback error signal in response to a readback error encountered during an external BIST operation.
6. The hierarchical memory of claim 1 , wherein the BIST main module is configured to perform external BIST operations in response to commands written to program input/output (PIO) registers in the hierarchical memory.
7. The hierarchical memory of claim 1 , wherein the test access interface comprises a Joint Test Action Group (JTAG) TAP controller.
8. The hierarchical memory of claim 1 , wherein the BIST slave modules are configured to place their associated memory blocks in a test mode upon receipt of a BIST enable signal from the BIST main module.
9. The hierarchical memory of claim 1 , wherein each of the memory blocks comprises a control logic circuit configured to interface with the common access bus, and wherein the BIST slave modules are configured to communicate with the BIST main module through the control logic circuit.
10. The hierarchical memory of claim 1 , wherein the BIST slave modules are configured to interface directly to the common access bus.
11. A method of performing Built-In Self Test (BIST) in a hierarchical memory, wherein the hierarchical memory includes a host bus interface coupled to a common access bus and wherein the host bus interface is configured to communicate with a plurality of memory blocks via the common access bus, the method comprising:
receiving test instructions from a test access interface, wherein the test access interface is coupled to the common access bus and wherein the test access interface is configured to communicate with at least one of the plurality of memory blocks via the common access bus; and
transmitting BIST control signals and test data to the at least one of the plurality of memory blocks over the common access bus in response to the test instructions.
12. The method of claim 11 , wherein transmitting BIST control signals and data comprises transmitting BIST control signals and test data from a BIST main module to a BIST slave module in the one of the plurality of memory blocks.
13. The method of claim 12 , further comprising:
executing BIST functions in the BIST slave module in response to the BIST control signals and test data provided by the BIST main module.
14. The method of claim 13 , wherein the BIST main module is configured to communicate with the BIST slave modules using a readback error signal that indicates a readback error in a memory block that is selected to return readback data, the method further comprising transmitting the readback error signal in response to a readback error encountered during an external BIST operation.
15. The method of claim 12 , further comprising placing the one of the plurality of memory blocks in a test mode upon receipt of a BIST enable signal from the BIST main module.
16. The method of claim 11 , further comprising receiving external test instructions through program input/output (PIO) registers in the memory, wherein transmitting BIST control signals and data to one of the plurality of memory blocks over the common access bus is performed in response to the external test instructions.
17. A hierarchical memory, comprising:
a common access bus;
a plurality of memory blocks coupled to the common access bus, wherein each of the plurality of memory blocks coupled to the common access bus includes a Built-In Self Test (BIST) slave module configured to receive BIST instructions and test data over the common access bus; and
a host bus interface coupled to the common access bus, wherein the host bus interface is configured to provide communication between an external host and a plurality of memory blocks over the common access bus.
18. The hierarchical memory of claim 17 , further comprising:
a test access port configured to receive test instructions and test data; and
a BIST main module coupled to the common access bus and configured to communicate with the plurality of memory blocks over the common access bus, to receive test data and configuration instructions from the test access port, and to provide BIST instructions to the BIST slave modules over the common access bus.
19. The hierarchical memory of claim 18 , wherein the BIST main module is configured to perform external BIST operations in response to commands written to program input/output (PIO) registers in the hierarchical memory.
20. The hierarchical memory of claim 18 , wherein each of the memory blocks comprises a control logic circuit configured to interface with the common access bus, and wherein the BIST slave modules are configured to communicate with the BIST main module through the control logic circuit.