IP Library Granted Patent US 7,643,958
Granted Patent B2
US 7,643,958 · App. 11/999,300 · Granted Jan 5, 2010

Method and system for validating PCI/PCI-X adapters

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Quick Facts
Patent No.
US 7,643,958
App. No.
11/999,300
Granted
Jan 5, 2010
Kind
B2
Abstract

An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters includes operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.

Claims (23)

1. An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters comprising:

a computer, said computer including

a motherboard

a PCI-X bus, and

an isolated test slot for operatively coupling a PCI/PCI-X adapter under test through said PCI-X bus to said motherboard, said isolated test slot being adapted and arranged to minimize degradation of data flow on said PCI-X bus such that a PCI-X adapter, mounted in said isolated test slot, can negotiate to a required operating rate which is greater than PCI operating rates, wherein said computer is operable to negotiate with and test a PCI or PCI-X bus adapter mounted in said isolated test slot at the required PCI or PCI-X operating rate, respectively; and

wherein said PCI/PCI-X adapter under test includes an internal register, said internal register receiving, through PCI/PCI-X negotiation, data representing the actual operating rate at which said PCI/PCI-X adapter has negotiated with said computer, and wherein said computer is operable to verify said PCI/PCI-X adapter is operating at said required PCI/PCI-X rate by comparing said data of said internal register with data representing an expected rate, predefined for said PCI/PCI-X adapter under test, loaded into said computer.

2. The system of claim 1 , wherein said computer is configured as a low profile system and wherein said isolated test slot is configured as a low profile slot.

3. The system of claim 2 , wherein said low profile system comprises a 2U low profile system.

4. The system of claim 1 , wherein said adapter mounted in said isolated test slot is a PCI-X bus adapter and wherein said required operating rate is at least 100 MHz.

5. The system of claim 1 , wherein said computer system is adapted and arranged to verify that the PCI or PCI-X adapter under test is operating at said required PCI or PCI-X rate, respectively.

6. A method of validating a Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters comprising:

operatively coupling a PCI/PCI-X adapter through a PCI-X bus to a motherboard of a computer, said PCI/PCI-X adapter including an internal register, and said coupling minimizing degradation of data flow on said PCI-X bus such that a PCI-X adapter can negotiate to a required operating rate which is greater than PCI operating rates,

negotiating a required operating rate of said coupled PCI/PCI-X bus adapter,

receiving at said internal register, through PCI/PCI-X negotiation, data representing the actual operating rate at which said PCI/PCI-X adapter has negotiated with said computer, and

testing the functionality of the PCI or PCI-X bus adapter at the required PCI or PCI-X operating rates, respectively; wherein testing the functionality of said PCI or PCI-X bus adapter comprises:

verifying said PCI/PCI-X adapter is operating at said required PCI/PCI-X rate by comparing said data of said internal register with data representing an expected rate, predefined for said PCI/PCI-X adapter under test, loaded into said computer.

7. The method of claim 6 , wherein said PCI/PCI-X adapter is operatively coupled to said motherboard by means of a low profile isolated test slot.

8. The method of claim 6 , wherein said PCI/PCI-X bus adapter is a PCI-X adapter and wherein said required operating rate is at least 100 MHz.

9. A computer program product comprising: a computer-usable data carrier storing instructions that, when executed by a computer, cause the computer to perform a method of validating a Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters comprising

operatively coupling a PCI/PCI-X adapter through a PCI-X bus to a motherboard of a computer, said PCI/PCI-X adapter including an internal register, and said coupling minimizing degradation of data flow on said PCI-X bus such that a PCI-X adapter can negotiate to a required operating rate which is greater than PCI operating rates,

negotiating a required operating rate of said coupled PCI/PCI-X bus adapter, and

testing the functionality of the PCI/PCI-X bus adapter at the required PCI or PCI-X operating rate, respectively; wherein testing the functionality of said PCI or PCI-X bus adapter comprises:

verifying said PCI/PCI-X adapter is operating at said required PCI/PCI-X rate by comparing said data of said internal register with data representing an expected rate, predefined for said PCI/PCI-X adapter under test, loaded into said computer.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →