Combined volatile nonvolatile array
View Patent ↗A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.
1. A memory circuit comprising:
volatile memory cells coupled to bit lines; and
nonvolatile memory cells coupled to the volatile memory cells via unswitched bit line connections, but not via complement bit lines.
2. The memory circuit of claim 1 , further comprising:
the volatile cells and the nonvolatile cells each coupled to a sense amplifier with level shifting capabilities, the volatile cells coupled to the sense amplifier via the bit lines and complement bit lines, and the nonvolatile cells coupled to the sense amplifier via the bit lines but not via the complement bit lines.
3. The memory circuit of claim 1 , wherein the volatile memory cells coupled to bit lines further comprise:
SRAM cells.
4. The memory circuit of claim 1 , wherein the volatile memory cells coupled to bit lines further comprise:
DRAM cells.
5. The memory circuit of claim 1 , wherein the volatile memory cells coupled to bit lines further comprise:
SRAM cells coupled to the bit lines and to complements of the bit lines.
6. The memory circuit of claim 1 , wherein the nonvolatile memory cells coupled to the volatile memory cells further comprises:
FLASH memory cells.
7. The memory circuit of claim 6 , wherein the FLASH memory cells further comprise:
FLASH cells comprising at least one SONOS transistor.
8. The memory circuit of claim 1 , wherein the nonvolatile memory cells coupled to the volatile memory cells further comprises:
each nonvolatile cell coupled to multiple volatile cells;
each nonvolatile cell coupled to a nonvolatile word line corresponding to a volatile word line; and
the volatile word line coupled to only one of the volatile cells to which the nonvolatile cell is coupled.
9. A computer system comprising:
a processor coupled to a memory circuit, the memory circuit comprising:
volatile memory cells coupled to bit lines;
nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines; and
nondifferential sense amplifiers coupled to bit lines.
10. The system of claim 9 , wherein the volatile memory cells coupled to bit lines further comprises:
SRAM cells.
11. The system of claim 9 , wherein the volatile memory cells coupled to bit lines further comprises:
SRAM cells coupled to the bit lines and to complements of the bit lines.
12. The system of claim 9 , wherein the nonvolatile memory cells coupled to the volatile memory cells further comprises:
FLASH memory cells coupled to the bit lines but not to complement bit lines.
13. The system of claim 12 , wherein the flash memory cells further comprise:
FLASH cells comprising at least one SONOS transistor.
14. The system of claim 9 , wherein the nonvolatile memory cells coupled to the volatile memory cells further comprises:
each nonvolatile cell coupled to multiple volatile cells;
each nonvolatile cell coupled to a nonvolatile word line corresponding to a volatile word line; and
the volatile word line coupled to only one of the volatile cells to which the nonvolatile cell is coupled.
15. A method of operating a memory circuit to store data from volatile memory to nonvolatile memory, comprising:
operating the volatile memory to cause data values stored in the volatile memory to be represented on bit lines; and
setting supply voltages of the nonvolatile memory to cause values from the bit lines to be stored by the nonvolatile memory without applying to the nonvolatile memory complements of the values represented on the bit lines.
16. The method of claim 15 , further comprising:
for each nonvolatile memory cell, operating a pair of transistors coupled between a bit line and the supply voltage for the cell.
17. The method of claim 16 , further comprising:
for each nonvolatile memory cell, operating at least one SONOS transistor.
18. The method of claim 16 , further comprising:
simultaneously asserting word lines for corresponding regions of the volatile and nonvolatile memories.
19. A method of operating a memory circuit to read data from nonvolatile memory to volatile memory, comprising:
operating the nonvolatile memory to cause data values stored in the nonvolatile memory to be represented on bit lines but not on complement bit lines;
passing the data values from the nonvolatile memory to the volatile memory via unswitched bit lines; and
operating a differential amplifier to cause the data values represented on the bit lines to be stored in the volatile memory.
20. The method of claim 19 , wherein operating the nonvolatile memory further comprises:
operating flash memory comprising at least one SONOS transistor per cell.
21. The method of claim 19 , further comprising:
simultaneously asserting word lines for corresponding regions of the volatile and nonvolatile memories.