IP Library Granted Patent US 8,598,717
Granted Patent B2
US 8,598,717 · App. 12/004,920 · Granted Dec 3, 2013

Semiconductor device and method for manufacturing the same

Inventor: Naomi Masuda (Kanagawa, JP)
Assignee: Spansion LLC
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Quick Facts
Patent No.
US 8,598,717
App. No.
12/004,920
Granted
Dec 3, 2013
Kind
B2
Abstract

A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.

Claims (28)

1. A semiconductor device comprising:

a plurality of semiconductor structures, each of the plurality of semiconductor structures comprising:

a semiconductor chip;

a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a cylindrical through electrode formed on an upper surface of the first land electrode that is electrically coupled to the first land electrode using a plurality of stud bumps wherein the plurality of stud bumps is formed between the through electrode and the land electrode wherein the diameter of the stud bumps is greater than the diameter of the cylindrical through electrode at the point at which the stud bumps and the cylindrical through electrode make contact; and

a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip,

wherein the bottom surface of the land electrode is coplanar with the bottom surface of the sealing resin and wherein a top surface and portions of side surfaces of the through electrode extend above the top surface of the sealing resin.

2. The semiconductor device according to claim 1 , wherein each of the plurality of semiconductor structures further comprises a second land electrode electrically coupled with the semiconductor chip, which is used for an external connection, wherein the connection electrode is provided around a periphery of the semiconductor chip, and the second land electrode is provided directly below the semiconductor chip.

3. The semiconductor device according to claim 1 , wherein in each of the plurality of semiconductor structures, an upper surface of the connection electrode is positioned higher than an upper surface of the sealing resin.

4. The semiconductor device according to claim 1 , wherein each of the plurality of semiconductor structures further comprises a wiring layer that is formed from a metal film and includes the first land electrode, the second land electrode and a wiring for electrically coupling the first and the second land electrodes.

5. The semiconductor device according to claim 1 , wherein in each of the plurality of semiconductor structures, the through electrodes formed on the first land electrodes which are adjacent with each other are positioned at different positions in a longitudinal direction of the first land electrode.

6. The semiconductor device according to claim 1 , wherein in each of the plurality of semiconductor structures, the wiring layer is positioned below a lower surface of the semiconductor chip which is positioned through a face-down packaging.

7. The semiconductor device according to claim 1 , wherein an adhesive agent bonds the first semiconductor structure to the second semiconductor structure vertically.

8. The semiconductor device according to claim 1 , wherein the first semiconductor structure and the second semiconductor structure are layered by bonding a first connection electrode of the first semiconductor device to a second connection electrode of the second semiconductor device.

9. The semiconductor device according to claim 8 , wherein another stud bump is formed between an upper surface of the first connection electrode and a lower surface of the second connection electrode.

10. The semiconductor device according to claim 8 , wherein the first and the second connection electrodes are bonded through thermocompression or soldering.

11. A system, comprising:

a processor;

a cache;

a user input component; and

a flash memory comprising:

a plurality of semiconductor structures, each of the plurality of semiconductor structures comprising:

a semiconductor chip;

a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a cylindrical through electrode formed on an upper surface of the first land electrode that is electrically coupled to the first land electrode using a plurality of stud bumps wherein the stud bump is formed between the through electrode and the land electrode wherein the diameter of the stud bumps is greater than the diameter of the cylindrical through electrode at the point at which the stud bumps and the through electrode make contact; and

a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip, wherein the bottom surface of the land electrode is coplanar with the bottom surface of the sealing resin and wherein a top surface and portions of side surfaces of the through electrode extend above the top surface of the sealing resin.

12. The system as recited in claim 11 wherein the system is a portable media player.

13. The system as recited in claim 11 wherein the system is a cellular telephone.

14. The system as recited in claim 11 wherein the system is a computing device.

15. The system according to claim 11 , wherein an adhesive agent bonds the first semiconductor structure to the second semiconductor structure vertically.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057072/0257 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2008
From: MASUDA, NAOMI
To: SPANSION LLC
Reel/Frame 020685/0527 →
Priority Claims (2)
JP 2006-353412 · Dec 27, 2006 · national
JP 2006/355025 · Dec 28, 2006 · national
Continuity (1)
Related Publication 20090026609A1 · Jan 29, 2009