Integrated circuit with reconfigurable inputs/outputs
View Patent ↗An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.
1. An integrated circuit (IC) device, comprising:
a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another;
a configuration circuit that selectively connects each signal path to a corresponding one of a plurality of physical connection points of the IC device according to one of at least two different physical orders in response to configuration information; wherein
the signal paths comprise data signal paths that carry sets of data values;
a parity generator circuit that generates parity values for selected data paths corresponding to the at least two different physical orders provided by the configuration circuit; and
a plurality of test storage circuits coupled to the plurality of signal paths that are operably connected to at least one test point accessible from an external connection of the integrated circuit device.
2. The integrated circuit device of claim 1 , wherein:
the plurality of signal paths comprises input signal paths to the core section.
3. The integrated circuit device of claim 1 , wherein:
the plurality of signal paths comprises output signal paths to the core section.
4. The integrated circuit device of claim 1 , wherein:
the signal paths comprise output data signal paths that carry sets of data values from the core section to the configuration circuit;
the configuration circuit connects the signal paths to the physical connection points in response to the configuration information; and
the parity generator circuit further includes a selector circuit that receives the generated parity values and outputs one of the parity values based on the configuration information.
5. The integrated circuit device of claim 1 , wherein:
the signal paths comprise input data signal paths that carry sets of data values from the configuration circuit to the core section; and
the configuration circuit connects the physical connection points to the signal paths in response to the configuration information, and provides a parity value to the core section.
6. The integrated circuit device of claim 1 , further including:
the configuration circuit connects the signal paths to the physical connection points in response to the configuration information; and
a configuration information storage circuit that stores the configuration information that is accessible from an external connection of the integrated circuit device.
7. The integrated circuit device of claim 1 , wherein:
the configuration circuit includes
a plurality of first signal lines coupled to the core section,
a plurality of second signal lines coupled to the physical connection points, and
a plurality of switch elements that selectively enable a signal path in response to configuration information, at least two switch elements being coupled between each first signal line and two second signal lines.
8. The integrated circuit device of claim 1 , wherein:
the configuration circuit includes
a plurality of first signal lines coupled to the core section,
a plurality of second signal lines coupled to the physical connection points, and
a plurality of logic circuits that selectively provide multiple paths between first signal lines and second signal lines in response to the configuration information.
9. The integrated circuit device of claim 8 , wherein:
the plurality of logic circuits includes output multiplexers (MUXs), each output MUX selectively coupling one of at least two second signal lines to at least one first signal line in response to the configuration information.
10. The integrated circuit device of claim 8 , wherein:
the plurality of logic circuits includes input multiplexers (MUXs), each input MUX selectively coupling one of at least two first signal lines to at least one second signal line in response to the configuration information.
11. The integrated circuit device of claim 1 , wherein:
the core section is coupled to the configuration circuit by a plurality of first signal paths and to the physical connection points by a plurality of second signal paths;
a first set of the first signal paths being selectively enabled in response to a first timing signal and a second set of the first signal paths being selectively enabled in response to a second timing signal; and
a first set of the second signal paths being selectively enabled in response to one timing signal selected from a plurality timing signals based on the configuration information, and a second set of the second signal paths being selectively enabled in response to another timing signal selected from the plurality timing signals based on the configuration information.
12. The integrated circuit device of claim 1 , further including:
a configuration physical connection point that provides at least a portion of the configuration information.
13. The integrated circuit device of claim 1 , wherein:
the configuration circuit selectively connects at least one group of paths to a corresponding group of physical connection points according to one of at least two different physical orders in response to the configuration information.
14. A method of making an integrated circuit design compatible with more than one package configuration, comprising the steps of:
forming at least one core portion in an integrated circuit substrate that executes a predetermined function;
forming a plurality of physical connection points on the integrated circuit substrate that provide signal paths for locations external to the integrated circuit substrate;
providing a reconfiguration section configurable to map signal paths from the at least one core portion to the plurality of physical connection points according to at least two different physical orders based on configuration information;
enabling different groups of signal paths between the core portion and the reconfiguration section in response to different clock signals; and
generating a different parity value for a same set of signals corresponding to each different physical order.
15. The method of claim 14 , further including:
selectively enabling different groups of signal paths between the reconfiguration section in response to one of the clocks signals selectable from all of the first clock signals according to configuration information.
16. An integrated circuit device having configurable inputs or outputs, comprising:
at least one core section that includes storage circuits that store data values including at least one array of content addressable memory cells including storage circuits that store data values for comparison with a received compare data value;
a plurality of physical connection points that allow external signal connection to be made to the integrated circuit; and
a configuration circuit coupled to the at least one core section by a plurality of first data signal paths, and coupled to a plurality of physical connection points by a plurality of second data signal paths, the configuration circuit including configurable signal paths that enable signals from the at least one core section to be coupled to the plurality of physical connections according to one of a plurality of different selectable physical orders.
17. The integrated circuit device of claim 16 , wherein:
the plurality of physical connection points comprise bond pads having an exposed conductive surface; and
the different selectable physical orders includes a first order of data signals and a second order of data signals that is a reverse of the first order.
18. The integrated circuit device of claim 16 , wherein:
the configuration circuit couples at least one group of first data signal paths, having a bit order with respect to one another, to a corresponding group of second data signal paths, and the different selectable physical orders are different bit orders of the second data signal paths with respect to one another.