IP Library Granted Patent US 7,964,446
Granted Patent B2
US 7,964,446 · App. 12/044,851 · Granted Jun 21, 2011

Semiconductor device and method of manufacturing the same

Assignee: Spansion LLC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,964,446
App. No.
12/044,851
Granted
Jun 21, 2011
Kind
B2
Abstract

A manufacturing method of a semiconductor device includes: forming a columnar electrode on a semiconductor wafer; flip-chip bonding a second semiconductor chip onto the semiconductor wafer; forming a molding portion on the semiconductor wafer, the molding portion covering and molding the columnar electrode and the second semiconductor chip; grinding or polishing the molding portion and the second semiconductor chip so that an upper face of the columnar electrode and an upper face of the semiconductor chip are exposed; and cutting the molding portion and the semiconductor wafer so that a first semiconductor chip, where the second semiconductor chip is flip-chip bonded and the columnar electrode is formed, is formed.

Claims (20)

1. A method for manufacturing a semiconductor device comprising:

forming a columnar electrode comprising a barrier electrode portion on a semiconductor wafer wherein the base of the columnar electrode is parallel with the top surface of the columnar electrode over a span that extends from a first to a second sidewall of the columnar electrode;

flip-chip bonding a second semiconductor chip onto the semiconductor wafer;

forming a molding portion on the semiconductor wafer, the molding portion covering and molding the columnar electrode and the second semiconductor chip;

grinding or polishing the molding portion and the second semiconductor chip so that an upper face of the barrier electrode and an upper face of the semiconductor chip are exposed wherein the upper face of the barrier electrode and the upper face of the second semiconductor chip are coplanar; and

cutting the molding portion and the semiconductor wafer so that a first semiconductor chip is formed where the second semiconductor chip is flip-chip bonded and the columnar electrode is formed.

2. The method as claimed in claim 1 , further comprising grinding or polishing a lower face of the semiconductor wafer.

3. The method as claimed in claim 1 , wherein the columnar electrode is electrically coupled to the first semiconductor chip and the second semiconductor chip.

4. The method as claimed in claim 1 , wherein the step of forming the columnar electrode comprises the step of forming the columnar electrode with an electrolytic plating method.

5. The method as claimed in claim 4 , wherein:

the step of forming the columnar electrode includes the step of forming a lower electrode and a barrier electrode on the semiconductor wafer with the electrolytic plating method; and

the step of grinding or polishing the molding portion includes the step of grinding or polishing the molding portion together with an upper portion of the barrier electrode.

6. The method as claimed in claim 5 , further comprising the step of forming a solder terminal on the barrier electrode.

7. The method as claimed in claim 4 , wherein the step of flip-chip bonding the second semiconductor chip is performed after the step of forming the columnar electrode.

8. The method as claimed in claim 1 , wherein the step of forming the columnar electrode comprises the step of forming the columnar electrode so as to be lower than the second semiconductor chip that is to be flip-chip bonded onto the semiconductor wafer.

9. The method as claimed in claim 1 , wherein the step of forming the molding portion includes the steps of:

forming a first resin portion so as to cover an area between an upper face of the semiconductor wafer and a lower face of the second semiconductor chip;

and forming a second resin portion on the first resin portion.

10. The method as claimed in claim 9 , wherein the step of forming the first resin portion includes the step of coating a liquid resin on the semiconductor wafer to form the first resin portion.

11. The method as claimed in claim 1 , further comprising the step of mounting the first semiconductor chip onto a mount portion.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0337 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2008
From: ONODERA, MASANORI; MEGURO, KOUICHI
To: SPANSION LLC
Reel/Frame 021061/0817 →
Priority Claims (1)
JP 2007-057828 · Mar 7, 2007 · national
Continuity (1)
Related Publication 20080217792A1 · Sep 11, 2008