Clock signal transmission circuit
View Patent ↗A clock signal transmission circuit having a variable initial value for a wait time that is required until a clock signal stabilizes. The clock signal is generated from an original clock signal. The wait time setting unit generates a plurality of wait time signals to wait until the original clock signal stabilizes before providing the clock signal to the internal circuit. A wait time determination unit selects one of the wait time signals and provides the selected wait time signal to a clock control unit. The wait time determination unit includes a data holding circuit which generates a selection signal in accordance with the initial value, a selection circuit which selects one of the wait time signals based on the selection circuit, and an initial value setting circuit enabling the initial value to be varied.
1. A clock signal transmission circuit for providing a clock signal to an internal circuit, the clock signal transmission circuit comprising:
a clock control unit which provides the internal circuit with the clock signal that is generated from an original clock signal;
a wait time setting unit which generates a plurality of wait time signals to wait until the original clock signal stabilizes before providing the clock signal to the internal circuit; and
a wait time determination unit which selects one of the plurality of wait time signals and provides the selected wait time signal to the clock control unit, the wait time determination unit including:
a data holding circuit which generates a selection signal in accordance with an initial value;
a selection circuit which selects one of the plurality of wait time signals based on the selection signal; and
an initial value setting circuit which variably sets the initial value of the data holding circuit.
2. The clock signal transmission circuit according to claim 1 , wherein the data holding circuit and the initial value setting circuit are operable as a scan shift circuit, and the initial value setting circuit includes a transfer control unit which transfers the initial value to the data holding circuit of the scan shift circuit.
3. The clock signal transmission circuit according to claim 2 , wherein the initial value is set by transferring scan data to the data holding circuit of the scan shift circuit.
4. The clock signal transmission circuit according to claim 2 , wherein the scan shift circuit includes a plurality of series-coupled register circuits, and the data holding circuit is at least one of the plurality of register circuits and arranged at the head of the plurality of register circuits.
5. The clock signal transmission circuit according to claim 4 , wherein the scan shift circuit is operable in a scan mode that uses first scan data and a transfer mode that uses second scan data, and the initial value setting circuit sets the initial value of the data holding circuit based on the second scan data in the transfer mode.
6. The clock signal transmission circuit according to claim 2 , wherein the transfer control unit includes:
a transfer mode setting unit which operates the scan shift circuit in a transfer mode; and
a clock transmission unit coupled to the transfer mode setting unit to provide the data holding circuit with a scan clock signal that is usable when transferring the initial value.
7. The clock signal transmission circuit according to claim 6 , wherein:
the transfer mode setting unit generates a transfer mode signal which operates the data holding circuit in the transfer mode based on a switching signal; and
the clock transmission unit includes a selector which provides the data holding circuit with the scan clock signal in response to the transfer mode signal.
8. The clock signal transmission circuit according to claim 6 , wherein the transfer control unit further includes:
a reset mask unit which prevents the initial value transferred to the data holding circuit from being reset until the clock control unit starts to provide the internal circuit with the clock signal in accordance with the selected wait time signal.
9. The clock signal transmission circuit according to claim 8 , wherein the reset mask unit includes:
a NOR circuit which receives a reset signal and a reset mask signal and generates a NOR signal; and
an OR circuit which receives the NOR signal and the reset mask signal and generates an OR signal that is capable of resetting the data holding circuit.
10. The clock signal transmission circuit according to claim 1 , wherein the wait time setting unit and the wait time determination unit are operated before the internal circuit is initialized.
11. A method for providing a clock signal to an internal circuit, the method comprising:
generating the clock signal from an original clock signal;
generating a plurality of wait time signals to wait until the original clock signal stabilizes before providing the clock signal to the internal circuit;
generating a selection signal which is used to select one of the plurality of wait time signals with a data holding circuit; and
setting a variable initial value for the selection signal of the data holding circuit with an initial value setting circuit before generating the selection signal.
12. The method according to claim 11 , further comprising:
operating the data holding circuit and the initial value setting circuit as a scan shift circuit;
wherein said setting an initial value for the selection signal includes transferring the initial value to the data holding circuit of the scan shift circuit.
13. The method according to claim 12 , wherein said setting an initial value for the selection signal includes transferring scan data to the data holding circuit of the scan shift circuit.
14. The method according to claim 11 , further comprising:
maintaining the initial value set for the data holding circuit until the clock signal is provided to the internal circuit in accordance with the wait time signal selected by the selection signal.