Sense amplifier with capacitance-coupled differential sense amplifier
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
1. A sense amplifier of a memory device comprising:
a first input;
a second input;
a first sense node;
a second sense node;
a first capacitive storage element comprising a first electrode communicatively coupled to the second input, and a second electrode; and
a first transistor comprising a control electrode communicatively coupled to the second electrode of the first capacitive storage element, a first current electrode selectively communicatively coupled to the first sense node and selectively communicatively coupled to the control electrode, and a second current electrode communicatively coupled to the first input.
2. The sense amplifier of claim 1 further comprising:
a second capacitive storage element selectively communicatively coupled in parallel across the first capacitive storage element.
3. The sense amplifier of claim 2 wherein a first electrode of the second capacitive storage element is selectively communicatively coupled to the second electrode of the second capacitive storage element.
4. The sense amplifier of claim 2 further comprising:
a first plurality of memory cells communicatively coupled to the first input; and
a second plurality of memory cells communicatively coupled to the second input.
5. The sense amplifier of claim 2 wherein the first input is selectively communicatively coupled to the second input.
6. The sense amplifier of claim 1 further comprising:
a first plurality of memory cells communicatively coupled to the first input; and
a second plurality of memory cells communicatively coupled to the second input.
7. The sense amplifier of claim 1 wherein the first input is selectively communicatively coupled to the second input.
8. The sense amplifier of claim 1 further comprising:
a voltage reference node to provide a fixed reference, and
wherein the first input is to be coupled to the fixed reference in response to a control signal, and the second input is to be coupled to the fixed reference in response to the control signal.
9. The sense amplifier of claim 8 further comprising:
a first plurality of memory cells communicatively coupled to the first input; and
a second plurality of memory cells communicatively coupled to the second input.
10. A sense amplifier of a memory device comprising:
a first input;
a second input;
a first sense node;
a second sense node;
a first capacitive storage element comprising a first electrode communicatively coupled to the second input, and a second electrode;
a first transistor comprising a control electrode communicatively coupled to the second electrode of the first capacitive storage element, a first current electrode selectively communicatively coupled to the first sense node, and a second current electrode communicatively coupled to the first input, the first current electrode of the first transistor selectively communicatively coupled to the control electrode of the first transistor;
a second capacitive storage element comprising a first electrode communicatively coupled to the first input, and a second electrode;
a second transistor comprising a control electrode communicatively coupled to the second electrode of the second capacitive storage element, a first current electrode selectively communicatively coupled to the second sense node, and a second current electrode communicatively coupled to the second input; and
a third capacitive storage element selectively communicatively coupled in parallel across the second capacitive storage element.
11. The sense amplifier of claim 10 further comprising:
a fourth capacitive storage element selectively communicatively coupled in parallel across the first capacitive storage element.
12. The sense amplifier of claim 11 wherein a first electrode of the fourth capacitive storage element is selectively communicatively coupled to the second electrode of the first capacitive storage element.
13. The sense amplifier of claim 11 , wherein the first current electrode of the second transistor is selectively communicatively coupled to the control electrode of the second transistor.
14. The sense amplifier of claim 10 , wherein the first current electrode of the second transistor is selectively communicatively coupled to the control electrode of the second transistor.
15. The sense amplifier of claim 10 further comprising:
a first plurality of memory cells communicatively coupled to the first input; and
a second plurality of memory cells communicatively coupled to the second input.
16. A sense amplifier of a memory device comprising:
a first input;
a second input;
a first sense node;
a second sense node;
a first capacitive storage element comprising a first electrode communicatively coupled to the second input, and a second electrode;
a first transistor comprising a control electrode communicatively coupled to the second electrode of the first capacitive storage element, a first current electrode selectively communicatively coupled to the first sense node and selectively communicatively coupled to the control electrode, and a second current electrode communicatively coupled to the first input; and
a second capacitive storage element selectively communicatively coupled in parallel across the first capacitive storage element.