IP Library Granted Patent US 7,859,040
Granted Patent B2
US 7,859,040 · App. 12/170,553 · Granted Dec 28, 2010

Non-volatile memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,859,040
App. No.
12/170,553
Granted
Dec 28, 2010
Kind
B2
Abstract

Non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface.

Claims (26)

1. A non-volatile memory unit, comprising:

a substrate having a source region, a drain region and a channel region, the channel region separates the source region and the drain region;

an electrically insulating layer adjacent to the source region, drain region and channel region layer;

a floating gate electrode adjacent to the electrically insulating layer, the electrically insulating layer separates the floating gate electrode from the channel region, the floating gate electrode having a floating gate major surface comprising a carbon based electron field emitter or a tungsten based field emitter;

a control gate electrode having a control gate major surface comprising a carbon based electron field emitter or a tungsten based field emitter, the control gate major surface opposing the floating gate major surface; and

a vacuum layer at least partially separating the control gate major surface from the floating gate major surface;

wherein the electrically insulating layer has a thickness value in a range from 1 to 5 nm separating the floating gate electrode from the substrate.

2. A non-volatile memory unit according to claim 1 , wherein the vacuum layer is a pressure of 1000 Pa or less.

3. A non-volatile memory unit according to claim 1 , wherein the vacuum layer has a thickness value in a range from 50 nm to 250 nm.

4. A non-volatile memory unit according to claim 1 , wherein electrons move between the control gate major surface and the floating gate major surface through the vacuum layer.

5. A non-volatile memory unit according to claim 1 , wherein the control gate major surface and the floating gate major surface comprise a diamond based electron field emitter.

6. A non-volatile memory unit according to claim 1 , wherein application of a first polarity voltage across the floating gate electrode and the control gate electrode moves electrons from the control gate electrode through the vacuum layer to the floating gate electrode.

7. A non-volatile memory unit according to claim 6 , wherein application of a second polarity voltage across the floating gate electrode and the control gate electrode moves electrons from the floating gate electrode through the vacuum layer to the control gate electrode, the second polarity voltage is an opposite polarity from the first polarity.

8. A non-volatile memory unit, comprising:

a substrate having a source region, a drain region and a channel region, the channel region separates the source region and the drain region;

an electrically insulating layer adjacent to the source region, drain region and channel region;

a floating gate electrode adjacent to the electrically insulating layer, the electrically insulating layer separates the floating gate electrode from the channel region, the floating gate electrode having a floating gate major surface comprising a carbon based electron field emitter or a tungsten based field emitter;

a control gate electrode having a control gate major surface comprising a carbon based electron field emitter or a tungsten based field emitter, the control gate major surface opposing the floating gate major surface; and

a gas layer at least partially separating the control gate electrode from the floating gate electrode;

wherein the electrically insulating layer has a thickness value in a range from 1 to 5 nm separating the floating gate electrode from the substrate.

9. A non-volatile memory unit according to claim 8 , wherein the gas layer comprises an inert gas.

10. A non-volatile memory unit according to claim 8 , wherein the gas layer comprises a noble gas.

11. A non-volatile memory unit according to claim 8 , wherein the gas layer has a thickness value in a range from 50 nm to 250 nm.

12. A non-volatile memory unit according to claim 8 , wherein electrons move between the gas layer and the floating gate major surface.

13. A non-volatile memory unit according to claim 8 , wherein application of a first polarity voltage across the floating gate electrode and the control gate electrode moves electrons from the gas layer to the floating gate electrode.

14. A non-volatile memory unit according to claim 13 , wherein application of a second polarity voltage across the floating gate electrode and the control gate electrode moves electrons from the floating gate electrode to the gas layer, the second polarity voltage is an opposite polarity from the first polarity.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jul 23, 2025
From: THE BANK OF NOVA SCOTIA
To: SEAGATE TECHNOLOGY PUBLIC LIMITED COMPANY; SEAGATE TECHNOLOGY; SEAGATE TECHNOLOGY HDD HOLDINGS; I365 INC.; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL; SEAGATE HDD CAYMAN; SEAGATE TECHNOLOGY (US) HOLDINGS, INC.
Reel/Frame 072193/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Recorded Jul 19, 2013
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT AND SECOND PRIORITY REPRESENTATIVE
To: SEAGATE TECHNOLOGY LLC; EVAULT INC. (F/K/A I365 INC.); SEAGATE TECHNOLOGY INTERNATIONAL; SEAGATE TECHNOLOGY US HOLDINGS, INC.
Reel/Frame 030833/0001 →
SECURITY AGREEMENT Recorded Mar 24, 2011
From: SEAGATE TECHNOLOGY LLC
To: THE BANK OF NOVA SCOTIA, AS ADMINISTRATIVE AGENT
Reel/Frame 026010/0350 →
RELEASE Recorded Jan 19, 2011
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: SEAGATE TECHNOLOGY HDD HOLDINGS; MAXTOR CORPORATION; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL
Reel/Frame 025662/0001 →
SECURITY AGREEMENT Recorded May 15, 2009
From: MAXTOR CORPORATION; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND FIRST PRIORITY REPRESENTATIVE; WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT AND SECOND PRIORITY REPRESENTATIVE
Reel/Frame 022757/0017 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2008
From: ZHENG, JUN
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 021228/0967 →