Low power content addressable memory
View Patent ↗A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.
1. A content addressable memory (CAM) device comprising:
an array having a plurality of columns of CAM cells, each column coupled to a number N of corresponding compare lines; and
a comparand mapping circuit having data inputs to receive a comparand value, data outputs coupled to the compare lines of the columns of CAM cells, and a control input to receive a mode select signal that selects between two different data mapping modes;
wherein the comparand mapping circuit provides the comparand value to the columns of CAM cells as sets of decoded signals if the mode select signal selects a first data mapping mode, and provides the comparand value to the columns of CAM cells as sets of complementary signals if the mode select signal selects a second data mapping mode.
2. The CAM device of claim 1 , wherein the comparand mapping circuit comprises a plurality of mapping sub-circuits, each having outputs coupled to the compare lines of a corresponding column of CAM cells and having an input to receive the mode select signal, and wherein during a first data mapping mode, each mapping sub-circuit decodes a respective group of bits of the comparand value into a corresponding set of decoded signals for output to a corresponding column of CAM cells, and during a second data mapping mode, each mapping sub-circuit outputs the respective group of bits of the comparand value to the corresponding column of CAM cells as complementary signals.
3. A content addressable memory (CAM) device comprising:
an array having a plurality of columns of CAM cells, each column coupled to a number N of corresponding compare lines; and
a comparand mapping circuit having data inputs to receive a comparand value, data outputs coupled to the compare lines of the columns of CAM cells, and a control input to receive a mode select signal that selects between two different data mapping modes;
wherein during a first data mapping mode, the comparand value is represented in the array by asserting only one of the N compare lines in each column of CAM cells, during a second data mapping mode, the comparand value is represented in the array by driving pairs of the N compare lines in each column of CAM cells to complementary states.
4. A content addressable memory (CAM) device comprising:
an array having a plurality of columns of CAM cells, each column coupled to a number N of corresponding compare lines;
a comparand mapping circuit having data inputs to receive a comparand value, data outputs coupled to the compare lines of the columns of CAM cells, and a control input to receive a mode select signal that selects between two different data mapping modes;
a write mapping circuit to convert an input data word into a converted data word having one of at least two different patterns of constituent bits according to the mode select signal; and
a read/write circuit coupled to receive the converted data word from the write mapping circuit and coupled to the array of CAM cells to output the converted data word thereto.
5. The CAM device of claim 4 , wherein the input data word includes data bits and mask bits with each of the data bits and mask bits constituting a respective data/mask bit pair, and wherein each set of four bits within the converted data word includes 2 R bits in a first state and the remaining bits in a second state if the mode select signal selects a first data mapping mode, R being the number of mask bits in a masking state within a group of two data/mask bit pairs.
6. The CAM device of claim 5 , wherein each set of four bits within the converted data word includes R-2 bits in a first state and the remaining bits in a second state if the mode select signal selects a second data mapping mode.
7. A content addressable memory (CAM) cell comprising:
an array of CAM cells, each including four storage elements and four switching circuits, each switching element coupled between a match line and a reference node, having a first input coupled to a respective one of the four storage elements, and having a second input coupled to a respective one of four compare lines; and
a plurality of comparand mapping sub-circuits each having data inputs to receive a portion of a comparand value, data outputs coupled to the compare lines of a corresponding column of CAM cells, and a control input to receive a mode select signal that determines whether the comparand value is provided to the array of CAM cells during compare operations in a decoded form or in a complementary form.
8. The CAM device of claim 7 , wherein during a first data mapping mode, each mapping sub-circuit decodes a respective group of bits of the comparand value into a set of decoded signals for output to a corresponding column of CAM cells, and during a second data mapping mode, each mapping sub-circuit outputs the respective group of bits of the comparand value to the corresponding column of CAM cells as complementary signals.
9. The CAM device of claim 8 , wherein during the first data mapping mode, the comparand value is represented in the array by asserting only one of the four compare lines associated with each column of CAM cells, and during the second data mapping mode, the comparand value is represented in the array by driving pairs of the four compare lines associated with each column of CAM cells to complementary states.
10. The CAM device of claim 7 , further comprising:
a write mapping circuit to convert an input data word into a converted data word having one of at least two different patterns of constituent bits according to the mode select signal; and
a read/write circuit coupled to receive the converted data word from the write mapping circuit and coupled to the array of CAM cells to output the converted data word thereto.
11. The CAM device of claim 10 , wherein the input data word includes data bits and mask bits with each of the data bits and mask bits constituting a respective data/mask bit pair, and wherein each set of four bits within the converted data word includes 2 R bits in a first state and the remaining bits in a second state if the mode select signal selects a first data mapping mode, R being the number of mask bits in a masking state within a group of two data/mask bit pairs.
12. The CAM device of claim 11 , wherein each set of four bits within the converted data word includes R-2 bits in a first state and the remaining bits in a second state if the mode select signal selects a second data mapping mode.
13. A method of operation within a content addressable memory (CAM) device including an array of CAM cells, the method comprising:
receiving a mode select signal;
receiving a comparand value;
providing the comparand value to the array as sets of decoded signals if the mode select signal selects a first comparand mapping mode; and
providing the comparand value to the array as sets of complementary signals if the mode select signal selects a second comparand mapping mode.
14. The method of claim 13 , wherein during the first data mapping mode, a comparand mapping circuit decodes a respective group of bits of the comparand value into a set of decoded signals, and during the second data mapping mode, the comparand mapping circuit outputs the respective group of bits of the comparand value to the corresponding column of CAM cells in complementary form.