IP Library Granted Patent US 7,692,941
Granted Patent B2
US 7,692,941 · App. 12/197,549 · Granted Apr 6, 2010

Separate CAM core power supply for power saving

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Quick Facts
Patent No.
US 7,692,941
App. No.
12/197,549
Granted
Apr 6, 2010
Kind
B2
Abstract

A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit chip, provides a first supply voltage to the first voltage supply pad, wherein the logic & control circuitry is powered by the first supply voltage. A second voltage supply, external to the integrated circuit chip, provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, wherein the second supply voltage is less than the first supply voltage.

Claims (56)

1. A content addressable memory (CAM) system comprising:

an integrated circuit chip including:

an array of CAM cells;

read/write access circuitry that performs read and write accesses to the array of CAM cells;

comparison access circuitry that performs comparison operations to the array of CAM cells;

a first voltage supply pad coupled to the read/write access circuitry; and

a second voltage supply pad coupled to the comparison access circuitry;

a first voltage supply, external to the integrated circuit chip, which provides a first supply voltage to the first voltage supply pad, wherein the read/write access circuitry is powered by the first supply voltage;

a second voltage supply, external to the integrated circuit chip, which provides a second supply voltage to the second voltage supply pad, wherein the comparison access circuitry is powered by the second supply voltage, and wherein the second supply voltage is less than the first supply voltage.

2. The CAM system of claim 1 , wherein the second voltage supply is an adjustable voltage supply.

3. The CAM system of claim 1 , wherein the CAM array is arranged in a plurality of rows and columns, wherein the comparison access circuitry comprises:

a plurality of match lines, each associated a corresponding row of CAM cells;

match line control circuitry powered by the second supply voltage, wherein the match line control circuitry pre-charges the match lines to the second supply voltage;

a plurality of search line pairs, each associated with a corresponding column of CAM cells;

search line control circuitry powered by the second supply voltage, wherein the search line control circuitry transmits search values on the search line pairs.

4. The CAM system of claim 3 , wherein the search values have a signal swing equal to the second supply voltage.

5. The CAM system of claim 4 , wherein the match lines have a signal swing equal to the second supply voltage.

6. The CAM system of claim 1 , wherein the CAM array is arranged in a plurality of rows and columns, wherein the read/write access circuitry comprises:

a plurality of word lines, each associated a corresponding row of CAM cells;

word line control circuitry powered by the first supply voltage, wherein the word line control circuitry drives word line signals onto the word lines;

a plurality of bit line pairs, each associated with a corresponding column of CAM cells;

bit line control circuitry powered by the first supply voltage, wherein the bit line control circuitry transmits data signals on the bit line pairs.

7. The CAM system of claim 6 , wherein the word line signals have a signal swing equal to the first supply voltage, and wherein the data signals have a signal swing equal to the first supply voltage.

8. A method of operating an integrated circuit chip including a content addressable memory (CAM) array, comprising:

powering read/write access circuitry that performs read and write accesses to the array of CAM cells with a first supply voltage;

powering comparison access circuitry that performs comparison operations within the array of CAM cells with a second supply voltage, wherein the second supply voltage is less than the first supply voltage;

providing the first supply voltage from a first power supply located external to the integrated circuit chip; and

providing the second supply voltage from a second power supply located external to the integrated circuit chip.

9. The method of claim 8 , further comprising adjusting the second supply voltage.

10. The method of claim 8 , further comprising pre-charging match lines of the comparison access circuitry to the second supply voltage.

11. The method of claim 10 , further comprising applying search data signals to search lines of the comparison access circuitry, wherein a first logic state of the search data signals corresponds with the second supply voltage.

12. The method of claim 8 , further comprising applying search data signals to search lines of the comparison access circuitry, wherein a first logic state of the search data signals corresponds with the second supply voltage.

13. The method of claim 8 , wherein the comparison access circuitry includes match lines that provide match results from the CAM array, and search lines that provide search data to the CAM array, the method further comprising operating the match lines and the search lines such that the signal swing on these lines does not exceed the second supply voltage.

14. The method of claim 8 , further comprising:

selecting a desired operating speed of the CAM array;

adjusting the second supply voltage to a minimum voltage that allows the CAM array to reliably operate at the desired operating speed.

15. The method of claim 8 , further comprising:

adjusting the second supply voltage to have a first voltage;

testing the CAM array while the second supply voltage is equal to the first voltage, thereby determining first operating characteristics of the CAM array at the first voltage;

adjusting the second supply voltage to have a second voltage, different than the first voltage;

testing the CAM array while the second supply voltage is equal to the second voltage, thereby determining second operating characteristics of the CAM array at the second voltage;

determining that the second operating characteristics are preferable to the first operating characteristics; and then

fixing the second supply voltage at the second voltage.

16. The method of claim 15 , wherein the step of determining that the second operating characteristics are preferable to the first operating characteristics comprises determining that the second operating characteristics include a lower power requirement than the first operating characteristics.

17. The method of claim 15 , wherein the step of determining that the second operating characteristics are preferable to the first operating characteristics comprises determining that the second operating characteristics include a faster operating speed than the first operating characteristics.

18. The method of claim 15 , wherein the step of determining that the second operating characteristics are preferable to the first operating characteristics comprises determining that the second operating characteristics include more reliable operation than the first operating characteristics.

19. A content addressable memory (CAM) system comprising:

an integrated circuit chip including:

logic and control circuitry;

an array of CAM cells;

read/write access circuitry that performs read and write accesses to the array of CAM cells;

comparison access circuitry that performs comparison operations to the array of CAM cells;

a first voltage supply pad coupled to the read/write access circuitry; and

a second voltage supply pad coupled to the comparison access circuitry;

a first voltage supply, external to the integrated circuit chip, which provides a first supply voltage to the first voltage supply pad, wherein the logic and control circuitry is powered by the first supply voltage;

a second voltage supply, external to the integrated circuit chip, which provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, and wherein the second supply voltage is less than the first supply voltage.

Assignments (12)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
RELEASE OF SECURITY INTEREST Recorded Aug 30, 2011
From: SILICON VALLEY BANK
To: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
Reel/Frame 026830/0141 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2009
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 022997/0607 →
SECURITY AGREEMENT Recorded Jul 17, 2009
From: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
To: SILICON VALLEY BANK
Reel/Frame 022973/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2008
From: CHU, SCOTT; PARK, KEE
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 021436/0397 →