IP Library Granted Patent US 7,952,177
Granted Patent B2
US 7,952,177 · App. 12/208,804 · Granted May 31, 2011

Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads

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Quick Facts
Patent No.
US 7,952,177
App. No.
12/208,804
Granted
May 31, 2011
Kind
B2
Abstract

A resin-sealed semiconductor device with built-in heat sink prevents internal bulging and cracking caused by exfoliation of a semiconductor element from the heat sink when the vapor pressure of moisture absorbed into a gap between the semiconductor element and the heat sink rises during mounting of the semiconductor device to a printed circuit board using lead-free solder. By providing a plurality of separated die pads ( 502 ) in a mounting area for a semiconductor element ( 301 ) and adhering the semiconductor element ( 301 ) to the heat sink ( 105 ) via the die pads ( 502 ), space is opened up between the semiconductor element ( 301 ) and the heat sink ( 105 ) for sealing resin ( 304 ) to run into.

Claims (53)

1. A semiconductor device comprising:

a lead frame having a plurality of inner leads;

a heat sink isolated from the lead frame, the heat sink being adhered to an underside of one end of each inner lead in an upper surface thereof;

a semiconductor element mounted on the upper surface of the heat sink;

a plurality of metallic wires electrically connecting the inner leads with corresponding electrode pads of the semiconductor element; and

a sealing resin that seals the inner leads, the semiconductor element and the metallic wires, wherein:

the semiconductor element is adhered to the upper surface of the heat sink in a plurality of bonded points by die bond,

a plurality of openings are provided in the heat sink, at least one of the plurality of openings being configured to extend to the semiconductor element and being arranged to overlap at least a central portion of the semiconductor element, and

when the heat sink is viewed in planar view, one of the bonded points is between at least one pair of the openings.

2. The semiconductor device of claim 1 , wherein

the openings in the heat sink are disposed to form a checkered pattern with the bonded points.

3. The semiconductor device of claim 1 , wherein

part of at least one of the openings in the heat sink is located outside a semiconductor mounting area.

4. The semiconductor device of claim 1 , wherein when the heat sink is viewed in planar view, the heat sink and the one end of each inner lead overlap.

5. The semiconductor device of claim 1 , wherein the at least one of the plurality of openings includes the sealing resin therein.

6. A semiconductor device, comprising:

a lead frame having a plurality of inner leads;

a heat sink isolated from the lead frame, the heat sink being adhered to an underside of one end of each inner lead in an upper surface thereof and having a plurality of openings formed therein;

a semiconductor element, at least one of the plurality of openings being configured to extend to the semiconductor element and being arranged to overlap at least a central portion of the semiconductor element, said semiconductor element being adhered to the upper surface of the heat sink via a die pad, the die pad being arranged such that, when the heat sink is viewed in planar view, the die pad is between a pair of the openings;

a plurality of metallic wires electrically connecting the inner leads with corresponding electrode pads of the semiconductor element; and

a sealing resin that seals the inner leads, the semiconductor element and the metallic wires.

7. The semiconductor device of claim 6 , wherein

part of at least one of the openings in the heat sink is located outside a semiconductor mounting area.

8. The semiconductor device of claim 6 , wherein

the semiconductor element and the upper surface of the heat sink are adhered to each other via a plurality of the die pads.

9. The semiconductor device of claim 8 , wherein

the openings in the heat sink are disposed to form a checkered pattern with the die pads.

10. The semiconductor device of claim 6 , further comprising:

a loop-shaped body that is encircled by a virtual line connecting the one end of each of the inner leads, and that surrounds a semiconductor mounting area,

wherein, formed extending inward on an inner edge of each side of the loop-shaped body in a central part of the side is a protrusion with a concave part formed on an outer edge of the side in a portion corresponding to the protrusion, and

the upper surface of the heat sink and an underside of the loop-shaped body are adhered to each other.

11. The semiconductor device of claim 6 , wherein when the heat sink is viewed in planar view, the heat sink and the one end of each inner lead overlap.

12. The semiconductor device of claim 6 , wherein the at least one of the plurality of openings includes the sealing resin therein.

13. A lead frame comprising:

a plurality of outer leads;

a plurality of inner leads coupled with the outer leads; and

a heat sink isolated from the lead frame, the heat sink being adhered to an underside of one end of each inner lead in an upper surface thereof, and having a plurality of openings formed at a semiconductor mounting area therein,

at least one of the plurality of openings being configured to extend to a semiconductor element and being arranged to overlap at least a central portion of the semiconductor element.

14. The lead frame of claim 13 , wherein

part of at least one of the openings in the heat sink is located outside the semiconductor mounting area.

15. The lead frame of claim 13 , further comprising:

a die pad attached to the upper surface of the heat sink, in the semiconductor mounting area on the upper surface of the heat sink,

wherein the openings are arranged such that, when the heat sink is viewed in planar view, the die pad is between a pair of the openings.

16. The lead frame of claim 15 , wherein

a plurality of the die pads are disposed on the upper surface of the heat sink.

17. The lead frame of claim 16 , wherein

the openings in the heat sink are disposed to form a checkered pattern with the die pads.

18. The lead frame of claim 13 , further comprising:

a loop-shaped body that is encircled by a virtual line connecting the one end of each of the inner leads, and that surrounds the semiconductor mounting area,

wherein, formed extending inward on an inner edge of each side of the loop-shaped body in a central part of the side is a protrusion with a concave part formed on an outer edge of the side in a portion corresponding to the protrusion, and

the upper surface of the heat sink and an underside of the loop-shaped body are adhered to each other.

19. The lead frame of claim 13 , wherein when the heat sink is viewed in planar view, the heat sink and the one end of each inner lead overlap.

20. The lead frame of claim 13 , wherein the at least one of the plurality of openings includes a sealing resin therein.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: PANNOVA SEMIC, LLC
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 037581/0466 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →