Gate protection diode for high-frequency power amplifier
A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n type region formed over the main surface of a p type epitaxial layer, a first p type region formed at the center of the main surface of the n type region, a second p type region formed over the main surface of the epitaxial layer around the n type region from the periphery of the main surface of the n type region, and p + type buried layers for coupling the second p type region to a substrate body. The distance between the end portions of the p + type buried layers and the n + type region is 7 μm or more.
1. A semiconductor device having a diode over a substrate comprising a substrate body of a first conductive type and a semiconductor layer of the first conductive type formed over the top of the substrate body,
wherein the diode comprises a first region of a second conductive type formed over the main surface of the semiconductor layer surrounded by a device separator, a second region of the first conductive type formed at the center of the main surface of the first region, a third region of the first conductive type formed over the main surface of the semiconductor layer surrounding the first region from the periphery of the main surface of the first region, and buried layers of the first conductive type which are buried in grooves formed in the semiconductor layer and couple the third region to the substrate body, and
wherein the buried layers are formed around the first region and have end portions formed by cutting on the planar shape, and the distance between the end portions of the buried layers and the first region is larger than the distance between portions other than the end portions of the buried layers and the first region.
2. The semiconductor device according to claim 1 , wherein the end portions of the buried layers are 7 μm or more away from the first region.
3. The semiconductor device according to claim 1 , wherein the impurity concentration of the substrate body is 1×10 19 to 1×10 20 cm −3 .
4. The semiconductor device according to claim 1 , wherein the resistivity of the substrate body is less than 3 mOcm.
5. The semiconductor device according to claim 1 , wherein the semiconductor layer surrounded by the device separator has a rectangular, square, polygonal or circular planar shape.
6. The semiconductor device according to claim 1 , wherein the planar shape of the semiconductor layer surrounded by the device separator is rectangular, and the buried layers have the end portions on both sides of the long sides of the first region along the long sides of the semiconductor layer surrounded by the device separator and the end portions on both sides of the short sides of the first region along the short sides of the semiconductor layer surrounded by the device separator.
7. The semiconductor device according to claim 6 , wherein the planar shape of the first region is rectangular without four corners.
8. The semiconductor device according to claim 6 , wherein the length of each of the buried layers along the long sides of the semiconductor layer is larger than the length of the first region along the long sides of the semiconductor layer.
9. The semiconductor device according to claim 6 , wherein the length of each of the buried layers along the short sides of the semiconductor layer is larger than the length of the first region along the short sides of the semiconductor layer.
10. The semiconductor device according to claim 1 , wherein the planar shape of the semiconductor layer surrounded by the device separator is rectangular, and the buried layers have end portions only on both sides of the long sides of the first region along the long sides of the semiconductor layer surrounded by the device separator.
11. The semiconductor device according to claim 1 , wherein the substrate further has a field effect transistor and the second region is electrically coupled to the gate of the field effect transistor.