IP Library Granted Patent US 7,777,473
Granted Patent B2
US 7,777,473 · App. 12/257,222 · Granted Aug 17, 2010

DC-DC converter and control circuit for DC-DC converter

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 7,777,473
App. No.
12/257,222
Granted
Aug 17, 2010
Kind
B2
Abstract

A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.

Claims (16)

1. A DC-DC converter comprising:

a first transistor receiving an input voltage;

a second transistor coupled to the first transistor;

a control circuit generating a first signal which controls the first transistor to turn on and off;

a comparator for detecting current flowing through the second transistor to generate a second signal which controls the second transistor, and for turning on the second transistor after a first period from the first transistor is turned off;

a variable voltage supply which applies an offset voltage to the comparator, the variable voltage supply setting the offset voltage to a first level when the DC-DC converter is powered down and setting the offset voltage to a second level after a given delay time elapses from when the DC-DC converter recovers to a normal operation from a power down operation; and

a pulse generation circuit for controlling the first signal and the second signal for turning off the second transistor during a second period from before the first transistor is turned on.

2. The DC-DC converter according to claim 1 , wherein the second period is greater than the first period.

3. A DC-DC converter comprising:

a first transistor receiving an input voltage;

a second transistor coupled to the first transistor;

a control circuit generating a first signal which controls the first transistor to turn on and off;

a comparator for detecting current flowing through the second transistor to generate a second signal which controls the second transistor to turn on and off;

a variable voltage supply which applies an offset voltage to the comparator, the variable voltage supply setting the offset voltage to a first level when the DC-DC converter is powered down and setting the offset voltage to a second level after a given delay time elapses from when the DC-DC converter recovers to a normal operation from a power down operation; and

a pulse generation circuit changing the first signal and the second signal,

wherein the second transistor is turned off before the first transistor is turned on, and the second transistor is turned on after each of the first transistor and the second transistor is turned off.

Assignments (11)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036042/0212 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →
CHANGE OF NAME Recorded Jun 4, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024484/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021977/0219 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2008
From: HASEGAWA, MORIHITO; TSUCHIYA, CHIKARA; ITO, HIDENOBU
To: FUJITSU LIMITED
Reel/Frame 021733/0523 →
Priority Claims (2)
JP 2005-373476 · Dec 26, 2005 · national
JP 2006-055904 · Mar 2, 2006 · national
Continuity (2)
Division 1143653400 · May 19, 2006
Related Publication 20090051339A1 · Feb 26, 2009