Resistive sense memory array with partial block update capability

1. A method comprising:

arranging a semiconductor array of resistive sense memory (RSM) cells into multi-cell blocks, each block having a physical block address (PBA);

writing a first set of user data to a selected block at a first PBA;

performing a partial block update operation by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA; and

reading the first and second blocks to retrieve the second set of user data and a remaining portion of the first set of user data.

2. The method of claim 1 , further comprising performing a bit set operation upon the second block prior to the performing step, wherein the bit set operation comprises selecting a bit set value from a plurality of bit set values each separately writable to said cells to place said cells in a selected resistive state, and writing the selected bit set value to each of the cells in the second block.

3. The method of claim 2 , further comprising a step of using a first bit set value for the second block, and performing the bit set operation upon a third block using a second bit set value different than the first bit set value.

4. The method of claim 1 , wherein the first and second blocks are each configured to store a common amount of user data.

5. The method of claim 1 , wherein each of the first and second blocks are divided into number of pages N, wherein the first set of user data of the writing step constitutes N pages of user data, wherein the second set of user data of the performing step constitutes N-M page of user data where M is less than N, and wherein the reading step comprises returning said N−M pages of user data from the second block and returning M pages of user data from the first block.

6. The method of claim 1 , wherein the first and second blocks are both associated with a common logical block address (LBA).

7. The method of claim 1 , wherein the first and second blocks are divided into a plurality of pages, each page comprising a user data field to store user data and an overhead field to store an update status for the associated user data in the user data field.

8. The method of claim 1 , further comprising a step of performing a second partial block update operation by writing a third set of user data to the second block at the second PBA wherein the third set of user data updates a portion of the second set of user data, and wherein the reading step further comprises retrieving the third set of user data from the second block.

9. The method of claim 1 , wherein the RSM cells are characterized as spin-torque transfer random access memory (STRAM) cells.

10. The method of claim 1 , wherein the RSM cells are characterized as resistive random access memory (RRAM) cells.

11. An apparatus comprising:

a non-volatile semiconductor memory array of resistive sense memory (RSM) cells arranged into multi-cell blocks, each block having an associated physical block address (PBA); and

a controller configured to direct a writing of a first set of user data to a selected block at a first PBA, to perform a partial block update operation by directing a writing of a second set of user data to a second block at a second PBA wherein the second set of user data updates a portion of the first set of user data in the first PBA, and to direct a reading of the first and second blocks to retrieve the second set of user data and the remaining portion of the first set of user data.

12. The apparatus of claim 11 , further comprising performing a bit set operation upon the second block prior to the performing step, wherein the bit set operation comprises selecting a bit set value from a plurality of bit set values each separately writable to said cells to place said cells in a selected resistive state, and writing the selected bit set value to each of the cells in the second block.

13. The apparatus of claim 12 , further comprising a step of using a first bit set value for the second block, and performing the bit set operation upon a third block using a second bit set value different than the first bit set value.

14. The apparatus of claim 11 , wherein the first and second blocks are each configured to store a common amount of user data.

15. The apparatus of claim 11 , wherein each of the first and second blocks are divided into number of pages N, wherein the first set of user data of the writing step constitutes N pages of user data, wherein the second set of user data of the performing step constitutes N−M page of user data where M is less than N, and wherein the reading step comprises returning said N−M pages of user data from the second block and returning M pages of user data from the first block.

16. The apparatus of claim 11 , wherein the first and second blocks are both associated with a common logical block address (LBA).

17. The apparatus of claim 11 , wherein the first and second blocks are divided into a plurality of pages, each page comprising a user data field to store user data and an overhead field to store an update status for the associated user data in the user data field.

18. The apparatus of claim 11 , further comprising a step of performing a second partial block update operation by writing a third set of user data to the second block at the second PBA wherein the third set of user data updates a portion of the second set of user data, and wherein the reading step further comprises retrieving the third set of user data from the second block.

19. The apparatus of claim 11 , wherein the RSM cells are characterized as spin-torque transfer random access memory (STRAM) cells.

20. The apparatus of claim 11 , wherein the RSM cells are characterized as resistive random access memory (RRAM) cells.