Method for generating performance evaluation model

1. A method for generating performance evaluation model comprising:

executing, by using first models of function modules which are described in a transaction level, a first simulation of system operation at the transaction level between the function modules;

recording transactions, which are generated in the first simulation per function module, by writing first data in a first portion of an interface register;

reading second data, which corresponds to a result obtained by performing a first function on the first data and was written in a second portion of the interface register, from the second portion;

executing, by using second models of the function modules which are described in a hardware level, a second simulation of circuit operation of each of the function modules to determine a delay time from the writing of the first data in the first portion to the reading of the second data from the second portion; and

assigning information of the delay time to the first model using a second function obtained by inserting information of the delay time to the first function and generating a third model per function module.

2. The method according to claim 1 , wherein the first model is described based on PV (Programmer's View), which performs design and verification in units of execution command of application software.

3. The method according to claim 1 , wherein the first model assigns, to the function module, an interface register and a function representing the operation of the function module.

4. The method according to claim 1 , wherein the second model is described based on RTL.

5. The method according to claim 1 , wherein the transaction is recorded in an interface register of the function module, and the delay time is assigned to the interface register.

6. The method according to claim 1 , wherein the transaction is at least one selected from a group of consisting of a data write operation and a data read operation.

7. A method for evaluating system performance, comprising:

executing, by using first models of function modules which are described in a transaction level, a first simulation of system operation at the transaction level between the function modules;

recording transactions, which are generated in the first simulation per function module, by writing first data in a first portion of an interface register;

reading second data, which corresponds to a result obtained by performing a first function on the first data and was written in a second portion of the interface register, from the second portion;

executing, by using second models of the function modules which are described in a hardware level, a second simulation of circuit operation of each of the function modules to determine a delay time from the writing of the first data in the first portion to the reading of the second data from the second portion;

assigning information of the delay time to the first model using a second function obtained by inserting information of the delay time to the first function and generating a third model per function module; and

executing, by using the third models, a third simulation of the system operation at the transaction level between the function modules to determine a processing time of the system operation.

8. The method according to claim 7 , wherein the first model is described based on PV (Programmer's View), which performs design and verification in units of execution command of application software.

9. The method according to claim 7 , wherein the first model assigns, to the function module, an interface register and a function representing the operation of the function module.

10. The method according to claim 7 , wherein the second model is described based on RTL.

11. The method according to claim 7 , wherein the transaction is recorded in an interface register of the function module, and the delay time is assigned to the interface register.

12. The method according to claim 7 , wherein the transaction is at least one selected from a group of consisting of a data write operation and a data read operation.

13. A system for generating a performance evaluation model and including an arithmetic processing unit which executes a program stored in a memory by a CPU and simulates function modules stored in the memory, wherein the arithmetic processing unit executes, by using first models of function modules which are described in a transaction level, a first simulation of system operation at the transaction level between the function modules;

records transactions which are generated in the first simulation per function module, by writing first data in a first portion of an interface register;

reads second data, which corresponds to a result obtained by performing a first function on the first data and was written in a second portion of the interface register, from the second portion;

executes, by using second models of the function modules which are described in a hardware level, a second simulation of circuit operation of each of the function modules to determine a delay time from the writing of the first data in the first portion to the reading of the second data from the second portion; and

assigns information of the delay time to the first model using a second function obtained by inserting information of the delay time to the first function and generates a third model per function module.

14. The system according to claim 13 , wherein the transaction recorded in the memory is expressed by recording write data and read data with respect to operation cycles.

15. The system according to claim 13 , wherein the first model is described based on PV (Programmer's View), which performs design and verification in units of execution command of application software.

16. The system according to claim 13 , wherein the first model assigns, to the function module, an interface register and a function representing the operation of the function module.

17. The system according to claim 13 , wherein the second model is described based on RTL.

18. The system according to claim 13 ,

wherein the arithmetic processing unit assigns an interface register to the function module,

wherein the transaction is recorded in the interface register of the function module, and

wherein the delay time is assigned to the interface register.

19. The system according to claim 13 , wherein the arithmetic processing unit executes, by using the third models, a third simulation of the system operation at the transaction level between the function modules to determine a processing time of the system operation.

20. The method according to claim 1 , further comprising:

selecting, when acquiring a plurality of delay times, the longest delay time from among the plurality of delay times; and

inserting information of the longest delay time to the second function.