Dynamic reconfigurable circuit with a plurality of processing elements, data network, configuration memory, and immediate value network

1. A dynamic reconfigurable circuit comprising:

a plurality of processing elements each provided with an arithmetic data input port, a configuration data input port and an output port;

a data network that is coupled to each of the arithmetic data input ports and each of the output ports of the plurality of processing elements;

a configuration memory that is coupled via a configuration path to the configuration data input port of a first processor element being at least one of the plurality of processing elements; and

an immediate value network that is independent from the data network and that is directly coupled to the configuration data input port of a second processor element being at least one of the plurality of processing elements,

wherein an internal register of a third processor element being at least one of the plurality of processing elements is coupled to the immediate value network so that data stored in the internal register can be outputted to the immediate value network, and

wherein a path to transfer data from the configuration memory to the second processor element via the immediate value network is independent from a path to transfer input data from an outside of the data network to the second processor element via the data network.

2. The dynamic reconfigurable circuit according to claim 1 ,

wherein the configuration data input port of the second processor element is coupled to both the configuration path and the immediate value network.

3. The dynamic reconfigurable circuit according to claim 2 ,

wherein the second processor element having the configuration data input port coupled to both the configuration path and the immediate value network selects an arithmetic function thereof based on data supplied via the configuration path from the configuration memory and uses data supplied from the immediate value network as an immediate value to perform an arithmetic operation.

4. The dynamic reconfigurable circuit according to claim 1 ,

wherein the configuration data input port of the second processor element is coupled only to the immediate value network and not to the configuration path.

5. The dynamic reconfigurable circuit according to claim 4 ,

wherein the second processor element having the configuration data input port coupled only to the immediate value network selects an arithmetic function thereof based on first data supplied from the immediate value network and uses second data supplied from the immediate value network as an immediate value to perform an arithmetic operation.

6. The dynamic reconfigurable circuit according to claim 1 ,

wherein the configuration data input port of the first processor element is coupled only to the configuration path and not to the immediate value network.

7. The dynamic reconfigurable circuit according to claim 1 ,

wherein no immediate value is stored in the configuration memory.

8. The dynamic reconfigurable circuit according to claim 1 ,

wherein the immediate value network is configured to change an interconnection between the processing elements.

9. The dynamic reconfigurable circuit according to claim 8 ,

wherein the interconnection configured by the immediate value network is set based on data stored in the configuration memory.

10. The dynamic reconfigurable circuit according to claim 1 ,

wherein a plurality of immediate values are stored in different addresses in the internal register of the third processor element.