Non-volatile two-transistor programmable logic cell and array layout
View Patent ↗A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
1. An array of non-volatile memory cells including:
a semiconductor body;
a plurality of switch-transistor wells disposed within the semiconductor body;
a plurality of memory-transistor wells disposed within the semiconductor body and electrically isolated from the memory-transistor wells, each memory-transistor well disposed between two switch-transistor wells;
a plurality of memory transistors formed within the plurality of memory transistor wells, each memory transistor including spaced-apart source and drain regions;
a first plurality of switch-transistors formed within each switch-transistor well, each switch transistor in the first plurality of switch transistors associated with one of the plurality of memory transistors in a memory-transistor well disposed to a first side of the switch-transistor well in which it is disposed and including spaced-apart source and drain regions;
a second plurality of switch-transistors formed within each switch-transistor well, each switch transistor in the second plurality of switch transistors associated with one of the plurality of memory transistors in a memory-transistor well disposed to a second side of the switch-transistor well in which it is disposed opposite to the first side and including spaced-apart source and drain regions;
a floating gate associated with each memory transistor, each floating gate insulated from and self-aligned with the source and drain regions of the memory transistor and each switch transistor with which it is associated;
and a control gate associated with each memory transistor, each control gate disposed above and self aligned with its floating gate and with the source and drain regions of the memory transistor and each switch transistor with which it is associated.
2. The array of non-volatile memory cells of claim 1 wherein:
at least some of the switch-transistors in each switch-transistor well are disposed in pairs by sharing one of a source region and a drain region.
3. The array of non-volatile memory cells of claim 2 , wherein:
source regions are shared between pairs of switch-transistors.
4. The array of non-volatile memory cells of claim 1 , wherein:
memory-transistor wells are optimized for memory-transistor characteristics and switch-transistor wells are optimized for switch-transistor characteristics.
5. The array of non-volatile memory cells of claim 1 , wherein:
memory-transistor wells are formed to different depths than switch-transistor wells.
6. The array of non-volatile memory cells of claim 1 wherein:
the semiconductor body is n-type;
the memory-transistor wells and the switch-transistor wells are all p-type wells;
and the memory-transistors and the switch-transistors are all n-channel transistors.
7. The array of non-volatile memory cells of claim 6 wherein:
the semiconductor body is an n-type well disposed in a p-type semiconductor substrate.
8. The array of claim 6 wherein each of the plurality of switch-transistor wells and memory-transistor wells disposed within the semiconductor body are electrically isolated from each other by an n-type isolation well having a first depth disposed within a p-type isolation well having a second depth greater than the first depth, the n-type isolation wells and p-type isolation wells disposed between and spaced apart from adjacent ones of the switch-transistor wells and the memory-transistor wells.
9. The array of claim 6 wherein each of the plurality of switch-transistor wells and memory-transistor wells disposed within the semiconductor body are electrically isolated from each other by an n-type isolation well, the n-type isolation wells disposed between and spaced apart from adjacent ones of the switch-transistor wells and the memory-transistor wells.
10. The array of claim 6 wherein each of the plurality of switch-transistor wells and memory-transistor wells disposed within the semiconductor body are electrically isolated from each other by a first n-type isolation well having a first depth disposed within a second n-type isolation well having a second depth greater than the first depth, the first and second n-type isolation wells disposed between and spaced apart from adjacent ones of the switch-transistor wells and the memory-transistor wells.
11. The array of claim 6 wherein each of the plurality of switch-transistor wells and memory-transistor wells disposed within the semiconductor body are electrically isolated from each other by:
a first p-type isolation well peripherally disposed at each switch-transistor well and each memory-transistor well;
an n-type isolation well having a first depth disposed within a second p-type isolation well having a second depth greater than the first depth, edges of the n-type isolation well and the second p-type isolation well abutting outer edges of the switch-transistor wells and each memory-transistor wells.
12. The array of claim 6 wherein each of the plurality of switch-transistor wells and memory-transistor wells disposed within the semiconductor body are electrically isolated from each other by shallow trench isolation regions.