Resistive sense memory calibration for self-reference read method
View Patent ↗Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
1. A method of calibrating a self-reference read of a resistive memory array, comprising:
setting a plurality of resistive memory units to a first resistive data state, the resistive memory units forming a memory array;
reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit; and
adjusting the first read current or the second read current for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
2. A method according to claim 1 wherein the resistive memory units comprise spin-transfer torque memory units.
3. A method according to claim 1 further comprising storing an adjusted first read current value or an adjusted second read current value for each resistive memory unit that utilized the adjusting step.
4. A method according to claim 1 wherein the second read current is greater than the first read current.
5. A method according to claim 4 wherein the first read current is 40% to 60% of the second read current.
6. A method according to claim 1 wherein the reading step comprises storing the voltage formed by the first read current in a first voltage storage device and storing the voltage formed by the second read current in a second voltage storage device and a third voltage storage device, the second voltage storage device and the third voltage storage device are electrically connected in series.
7. A method according to claim 6 wherein comparing the voltage formed by the first read current with the voltage formed by the second read current further comprises sensing the stored second voltage at an intermediate node electrically between the second voltage storage device and the third voltage storage device.
8. A method according to claim 1 wherein the adjusting step comprises increasing or decreasing the first read current or second read current with an adjustable current mirror.
9. A method according to claim 8 wherein the adjusting step comprises adjusting a mirror ratio of the adjustable current mirror to modify the first read current or the second read current.
10. A method according to claim 9 further comprising storing the adjusted mirror ratio of the adjustable current mirror for each resistive memory unit that utilized the adjusting step.
11. A method according to claim 1 wherein the reading step does not change a data state of the resistive memory unit.
12. A method of calibrating a self-reference read of a resistive memory array, comprising:
setting a plurality of resistive sense memory units to a first resistive data state, the resistive sense memory units forming a memory array;
reading a sensed resistive data state for each resistive sense memory unit by applying a first read current and a second read current through each resistive sense memory unit and then storing a first read voltage formed by the first read current in a first voltage storage device and storing a second read voltage formed by the second read current in a second voltage storage device and then comparing the first read voltage with the second read voltage to determine the sensed resistive data state for each resistive sense memory unit; and
adjusting capacitance of the first or second voltage storage device for each resistive sense memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
13. A method according to claim 12 wherein the first voltage storage device comprises a first capacitor and the second voltage storage device comprises a second capacitor and a third capacitor, the second capacitor and the third capacitor are electrically connected in series.
14. A method according to claim 13 wherein the second voltage storage device includes at least a fourth capacitor selectively electrically connected with the second capacitor and the third capacitor.
15. A method according to claim 13 wherein the reading step comprises comparing the first read voltage with the second read voltage and the stored second voltage is sensed at an intermediate node electrically between the second capacitor and the third capacitor.
16. A method according to claim 12 wherein the resistive sense memory unit comprises RRAM.
17. A method according to claim 12 further comprising storing an adjusted capacitance of the first or second voltage storage device for each resistive sense memory unit that utilized the adjusting step.
18. A method of calibrating a self-reference read of a resistive memory array, comprising:
setting a plurality of resistive memory units to a first resistive data state, the resistive memory units forming a memory array;
reading a sensed resistive data state for each resistive memory unit by applying a first read voltage and a second read voltage across each resistive memory unit and then comparing the first read voltage with the second read voltage to determine the sensed resistive data state for each resistive memory unit; and
adjusting the first or second read voltage for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
19. A method according to claim 18 further comprising storing an adjusted first or second read voltage for each resistive sense memory unit that utilized the adjusting step.
20. A method according to claim 18 wherein the reading step does not change a data state of the resistive memory unit.
21. A resistive memory apparatus, comprising:
an array of resistive memory units;
a self-reference read circuit comprising an electrical adjustment circuit for adjusting an electrical property of the self-reference read circuit so that sensed resistive data can be adjusted until the sensed resistive data state is the same as a predetermined first resistive data state for each resistive memory unit.
22. A resistive memory apparatus according to claim 21 , wherein the electrical adjustment circuit comprises an adjustable read current source.
23. A resistive memory apparatus according to claim 21 , wherein the electrical adjustment circuit comprises an adjustable read voltage source.
24. A resistive memory apparatus according to claim 21 , wherein the electrical adjustment circuit comprises a voltage storage device having an adjustable capacitance.