Antifuses with curved breakdown regions
View Patent ↗An antifuse ( 40, 80, 90 ′) comprises, first ( 22′, 24′ ) and second ( 26 ′) conductive regions having spaced-apart curved portions ( 55, 56 ), with a first dielectric region ( 44 ) therebetween, forming in combination with the curved portions ( 55, 56 ) a curved breakdown region ( 47 ) adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region ( 42 ) is desirably provided adjacent the breakdown region ( 47 ) to inhibit heat loss from the breakdown region ( 47 ) during programming. Lower programming voltages and currents are observed compared to antifuses ( 30 ) using substantially planar dielectric regions ( 32 ). In a further embodiment, a resistive region ( 922 ) is inserted in one lead ( 92, 92 ′) of the antifuses ( 90, 90 ′) with either planar ( 37 ) or curved ( 47 ) breakdown regions to improve post-programming sense reliability.
1. An antifuse, comprising:
first and second conductive regions having spaced-apart curved portions; and
a first dielectric region separating the spaced-apart curved portions, thereby forming in combination with the curved portions a curved breakdown region adapted to switch from a substantially non-conductive state to a substantially conductive state in response to a predetermined applied programming voltage.
2. The antifuse of claim 1 , wherein the first and second conductive regions are doped semiconductor regions.
3. The antifuse of claim 2 , wherein the second conductive region is a substantially polycrystalline semiconductor region and the first conductive region is a substantially single crystal semiconductor region.
4. The antifuse of claim 2 , further comprising a second dielectric region substantially thicker than the first dielectric region located adjacent the first dielectric region at first ends of the curved portions.
5. The antifuse of claim 4 , further comprising a semiconductor substrate, wherein the first and second conductive regions are formed by doping of the substrate, and the first dielectric region is formed by oxidation of the substrate.
6. The antifuse of claim 5 , wherein the second dielectric region comprises a dielectric filled cavity in the substrate.
7. The antifuse of claim 1 , wherein the first dielectric region is a thermally grown oxide region.
8. The antifuse of claim 4 , wherein the second dielectric region comprises a dielectric formed by chemical vapor deposition.
9. The antifuse of claim 4 , where in the second dielectric region comprises a dielectric formed in part by thermal oxidation and in part by deposition.
10. An antifuse having first and second terminals, comprising:
a substrate having a first surface;
a first conductive region adjacent the first surface and coupled to the first terminal;
a dielectric region in contact with the first conductive region;
a second conductive region having a first portion overlying the dielectric region, a second portion spaced apart from the dielectric region and a third portion spaced apart from the second portion and the dielectric region;
a first contact coupled to the second terminal and ohmically coupled to the first portion of the second conductive region;
a second contact coupled to the second terminal and ohmically coupled to the third portion of the second conductive region; and
wherein the first portion of the second conductive region provides a first resistance between the first contact and the dielectric region, and the second portion of the second conductive region provides a second resistance between the second contact and the dielectric region, wherein the second resistance is higher than the first resistance.
11. The antifuse of claim 10 , wherein the dielectric region is substantially planar.
12. The antifuse of claim 10 , wherein the dielectric region is curved.
13. The antifuse of claim 12 , wherein the dielectric region has a thickness of about 1 to 10 nanometers.
14. The antifuse of claim 10 , wherein the second conductive region is a doped semiconductor and the second portion has a lower doping than the first and third portions.
15. An antifuse comprising: a substrate having an upper surface; a dielectric formed within a cavity extending a predetermined distance into the substrate from the upper surface, the dielectric having a central region depressed from the upper surface;
a curved dielectric region on a curved portion of the upper surface of the substrate adjacent the cavity and extending toward the central region; and
a conductor having a curved portion overlying the curved dielectric region, thereby forming a breakdown region comprising the curved portion of the conductor and the curved portion of the substrate on either side of the curved dielectric region.
16. The antifuse of claim 15 , wherein the curved dielectric region has a thickness in a range of 1 to 10 nanometers.