Head gimbal assembly without bus traces for plating
Head gimbal assemblies for data storage systems are provided. Some embodiments include a dielectric layer having a first and a second side. A first conductive layer is on the first dielectric layer. The first conductive layer includes a pad and a trace. A second conductive layer is on the second dielectric side. A via extends from the first dielectric layer side to the second dielectric layer side. The via electrically connects the first conductive layer to the second conductive layer.
1. A head gimbal assembly for a data storage system comprising:
a dielectric layer having a first and a second side;
a first conductive layer on the first dielectric side, the first conductive layer having a pad and a trace;
a second conductive layer on the second dielectric side, the second conductive layer comprising an island; and
a via that is electrically connected to the island and extends from the first dielectric layer side to the second dielectric layer side, and wherein the via electrically connects the first conductive layer to the second conductive layer.
2. The head gimbal assembly of claim 1 wherein the via is electrically connected to the pad.
3. The head gimbal assembly of claim 1 wherein the via is electrically connected to the trace.
4. The head gimbal assembly of claim 1 , wherein the second conductive layer further comprises a second island and wherein the first and second islands are electrically isolated from each other.
5. The head gimbal assembly of claim 1 wherein the first conductive layer comprises copper and the second conductive layer comprises stainless steel.
6. The head gimbal assembly of claim 1 wherein the first conductive layer further comprises a second pad and a second trace.
7. The head gimbal assembly of claim 1 , further comprising a coverlay layer at least partially covering a portion of the trace, wherein the dielectric layer and the coverlay layer comprise polyimide.
8. A head gimbal assembly circuit for a data storage system comprising:
an electrically conductive pad;
an electrically conductive trace, wherein the trace is electrically connected to the pad;
a dielectric layer;
an electrically conductive island, wherein the island is separated from the pad and the trace by the dielectric layer; and
an electrically conductive via, wherein the electrically conductive via passes through the dielectric layer and electrically connects the island to the pad and the trace.
9. The head gimbal assembly circuit of claim 8 and further comprising:
a second electrically conductive pad;
a second electrically conductive trace, wherein the second trace is electrically connected to the second pad;
a second electrically conductive island, wherein the second island is separated from the second pad and the second trace by the dielectric layer; and
a second electrically conductive via, wherein the second electrically conductive via passes through the dielectric layer and electrically connects the second island to the second pad and the second trace.
10. The head gimbal assembly circuit of claim 9 wherein the islands are electrically isolated from one another.
11. The head gimbal assembly circuit of claim 9 wherein the traces are electrically isolated from one another.
12. The head gimbal assembly circuit of claim 9 wherein the pads are electrically isolated from one another.
13. The head gimbal assembly circuit of claim 8 and further comprising a coverlay layer that covers at least a portion of the trace.
14. The head gimbal assembly circuit of claim 8 wherein the trace comprises copper.
15. The head gimbal assembly circuit of claim 14 wherein the trace further comprises gold.
16. A data storage system comprising:
a read/write head;
a system electrical component;
a circuit connected to the read/write head and to the system electrical component, wherein the circuit transmits electrical signals between the read/write head and the system electrical component and wherein the circuit is at least partially electrically isolated by a dielectric layer;
an aperture in the dielectric layer; a via, wherein the via is located at least partially within the aperture in the dielectric layer and wherein the via is electrically connected to at least a portion of the circuit;
a second aperture in the dielectric layer; and
a second via, wherein the second via is located at least partially within the second aperture in the dielectric layer, wherein the second via is electronically connected to at least a portion of the circuit, and wherein the vias are electrically isolated from each other.