Method and apparatus for universal program controlled bus architecture
View Patent ↗An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
1. A field programmable gate array integrated circuit device, comprising:
(a) a core comprising a plurality of configurable logic blocks coupled to a plurality of programmable interconnects, wherein one of the plurality of configurable logic blocks is configured as a programmable interface;
(b) a plurality of I/O logic blocks programmably coupleable to the core;
(c) a plurality of megacells, each megacell programmably coupleable to a first programmable bus via the programmable interface, wherein a first set of the plurality of programmable interconnects programmably couple the programmable interface to the plurality of megacells; and
(d) a second programmable bus coupled to
(i) the first programmable bus; and
(ii) the I/O logic blocks.
2. The field programmable gate array integrated circuit device of claim 1 , wherein the second programmable bus is programmably coupled to the first programmable bus.
3. The field programmable gate array integrated circuit device of claim 1 , wherein the second programmable bus is hardwired to the first programmable bus.
4. The field programmable gate array integrated circuit device of claim 1 , wherein the second programmable bus is programmably coupleable to the core.
5. A field programmable gate array integrated circuit device, comprising:
(a) a core comprising a plurality of configurable logic blocks coupled to a plurality of programmable interconnects;
(b) a plurality of I/O logic blocks programmably coupleable to the core;
(c) a plurality of megacells, each megacell programmably coupleable to a first programmable bus via a programmable interface; and
(d) a second programmable bus coupled to
(i) the first programmable bus; and
(ii) the I/O logic blocks, wherein each megacell is programmably coupleable to the second programmable bus via a programmable interface.
6. The field programmable gate array integrated circuit device of claim 1 , wherein the first programmable bus is programmably coupleable to the core via a programmable interface.
7. The field programmable gate array integrated circuit device of claim 1 , further comprising a plurality of gateway logic blocks coupled between at least one I/O logic block and the core.
8. The field programmable gate array integrated circuit device of claim 7 , wherein:
(a) the second programmable bus is programmably coupleable to the core; and
(b) the second programmable bus is programmably coupleable to the gateway logic blocks.
9. The field programmable gate array integrated circuit device of claim 7 , wherein the gateway logic blocks are programmably coupleable to the core via the second programmable bus.
10. The field programmable gate array integrated circuit device of claim 9 , wherein each megacell is programmably coupleable to the second programmable bus via a programmable interface.
11. The field programmable gate array integrated circuit device of claim 9 , wherein the first programmable bus is programmably coupleable to the core via a programmable interface.
12. The field programmable gate array integrated circuit device of claim 8 , wherein each megacell is programmably coupleable to the second programmable bus via a programmable interface.
13. The field programmable gate array integrated circuit device of claim 8 , wherein the first programmable bus is programmably coupleable to the core via a programmable interface.
14. The field programmable gate array integrated circuit device of claim 5 , wherein the second programmable bus is programmably coupled to the first programmable bus.
15. The field programmable gate array integrated circuit device of claim 5 , wherein the second programmable bus is programmably coupleable to the core.
16. The field programmable gate array integrated circuit device of claim 5 , wherein the first programmable bus is programmably coupleable to the core via a programmable interface.
17. The field programmable gate array integrated circuit device of claim 5 , further comprising a plurality of gateway logic blocks coupled between at least one I/O logic block and the core.
18. The field programmable gate array integrated circuit device of claim 17 , wherein:
(a) the second programmable bus is programmably coupleable to the core; and
(b) the second programmable bus is programmably coupleable to the gateway logic blocks.
19. A field programmable gate array integrated circuit device, comprising:
(a) a core comprising a plurality of configurable logic blocks coupled to a plurality of programmable interconnects;
(b) a plurality of I/O logic blocks programmably coupleable to the core;
(c) a plurality of megacells, each megacell programmably coupleable to a first programmable bus via a programmable interface;
(d) a second programmable bus coupled to
(i) the first programmable bus; and
(ii) the I/O logic blocks; and
(e) a plurality of gateway logic blocks coupled between at least one I/O logic block and the core, wherein each megacell is programmably coupleable to the second programmable bus via a programmable interface.
20. The field programmable gate array integrated circuit device of claim 19 , wherein the gateway logic blocks are programmably coupleable to the core via the second programmable bus.