Stuck-at defect condition repair for a non-volatile memory cell
View Patent ↗A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
1. A memory device comprising:
a resistive sense element having a magnetic tunneling junction (MTJ); and
a repair plane adjacent to a plurality of the resistive sense elements and aligned with a long axis of at least one resistive sense element to inject a magnetic field in the MTJ to repair a stuck-at defect condition.
2. The memory device of claim 1 , wherein the MTJ comprises a fixed magnetic layer and a free magnetic layer coupled to a tunneling barrier.
3. The memory device of claim 2 , wherein the repair plane is adjacent the free magnetic layer of the MTJ.
4. The memory device of claim 1 , wherein the repair plane is partially surrounded by a soft magnetic material.
5. The memory device of claim 1 , wherein the repair plane repairs the MTJ after a failed write verify operation.
6. The memory device of claim 1 , wherein the repair plane repairs the MTJ after successively increasing the write current passed through the resistive sense element to a predetermined threshold.
7. The memory device of claim 1 , wherein resistive sense element is spin-torque transfer random access memory (STRAM).
8. A method comprising:
providing a plurality of resistive sense elements each having a magnetic tunneling junction (MTJ); and
repairing a stuck-at defect condition by injecting a magnetic field in the MTJ using a repair plane adjacent to and spanning a plurality of the resistive sense elements.
9. The method of claim 8 , wherein the MTJ comprises a fixed magnetic layer and a free magnetic layer coupled to a tunneling barrier.
10. The method of claim 9 , wherein the repair plane is adjacent the free magnetic layer of the MTJ.
11. The method of claim 8 , wherein the repair plane is aligned with a long axis of the resistive sense element.
12. The method of claim 8 , wherein the repair plane is aligned with a short axis of the resistive sense element.
13. The method of claim 8 , wherein the repair plane repairs the MTJ after a failed write verify operation.
14. The method of claim 8 , wherein the repair plane repairs the MTJ after successively increasing the write current passed through the resistive sense element to a predetermined threshold.
15. The method of claim 8 , wherein the repairing step comprises applying a current pulse to the repair plane to induce said magnetic field in the MTJ.
16. A memory array comprising:
a resistive sense element having a magnetic tunneling junction (MTJ); and
a repair plane adjacent a plurality of the resistive sense elements and aligned with a short axis of at least one of the resistive sense elements, the repair plane injecting a magnetic field in the MTJ to repair a stuck-at defect condition.
17. The memory array of claim 16 , wherein the repair plane is proximal to a magnetic free layer and distal to a magnetically fixed layer of a resistive sense element.
18. A method comprising:
providing a resistive sense element each having a magnetic tunneling junction (MTJ); and
repairing a stuck-at defect condition by injecting a magnetic field in the MTJ using a repair plane that is at least partially surrounded by a soft magnetic material and is adjacent the resistive sense element.
19. The method of claim 18 , wherein at least one resistive sense element is deallocated in response to the stuck-at defect condition being present after the repairing step.