Asymmetric write current compensation

1. An apparatus comprising a nonvolatile unit cell comprising a switching device coupled to an asymmetric resistive sense element (RSE), wherein the RSE is oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell to compensate for write current asymmetry in the unit cell.

2. The apparatus of claim 1 , wherein the RSE is physically oriented relative to the switching device within the unit cell such that the hard direction for programming the RSE comprises a first direction in which a first write current is required through the RSE to set the RSE to a first resistive state, wherein the easy direction for programming the RSE comprises a second direction opposite the first direction in which a second write current is required through the RSE to set the RSE to a different, second resistive state, and wherein the first write current is greater in magnitude than the second write current.

3. The apparatus of claim 2 , wherein the switching device is connected in series with the RSE between a first control line and a second control line, wherein the easy direction for programming the unit cell corresponds to a respective sequencing of the RSE and the switching device such that the first write current passes from the first control line, through the RSE and then through the switching device to the second control line.

4. The apparatus of claim 3 , wherein the hard direction for programming the unit cell corresponds to a respective sequencing of the RSE and the switching device such that the second write current passes from the second control line, through the switching device and then through the RSE to the first control line.

5. The apparatus of claim 1 , wherein the switching device comprises a transistor having a drain-to-source conductive path in series with the RSE, wherein in the hard direction for programming the unit cell a first write current passes through the drain-to-source conduction path prior to passing through the RSE, and wherein in the easy direction for programming the unit cell a second write current passes through the RSE prior to passing through the drain-to-source conduction path.

6. The apparatus of claim 1 , wherein the RSE is characterized as a magnetic tunneling junction (MTJ) comprising a reference layer with a fixed direction of magnetization and a free layer with a selectively changeable direction of magnetization, wherein the MTJ is programmed to a first resistive state when the direction of magnetization of the free layer is set to be parallel to the direction of magnetization of the reference layer, wherein the MTJ is programmed to a second resistive state when a direction of magnetization of the free layer is set to be anti-parallel to the direction of magnetization of the reference layer, and wherein the MTJ is physically oriented within the unit cell with respect to the switching device such that a selected write current applied to the unit cell successively passes through the switching device, through the free layer and then through the reference layer.

7. The apparatus of claim 1 , wherein the RSE is characterized as a resistive random access memory (RRAM) element.

8. The apparatus of claim 1 , further comprising a first write driver which applies a first write current in a first direction through the unit cell to program the RSE to a first resistive state, and a second write driver which applies a second write current in a second direction through the unit cell to program the RSE to a second resistive state, wherein the first write current has a magnitude that is substantially equal to a magnitude of the second write current.

9. The apparatus of claim 1 , wherein the RSE is configured to store a first multi-bit value when programmed in the easy direction of programming the unit cell, and wherein the RSE is configured to store a second multi-bit value when programmed in the hard direction of programming the unit cell.

10. A method comprising compensating for write current asymmetry in a nonvolatile unit cell by orienting an asymmetric resistive sense element (RSE) of the unit cell relative to a switching device of the unit cell such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

11. The method of claim 10 , wherein the compensating step further comprises programming the RSE to a first resistive state by applying a first write current through the unit cell in the easy direction of programming the unit cell, and programming the RSE to a different, second resistive state by applying a second write current through the unit cell in the hard direction of programming the unit cell, wherein the first write current has a magnitude that is substantially the same as a magnitude of the second write current.

12. The method of claim 10 , wherein the hard direction for programming the RSE comprises a first direction in which a first write current is applied through the RSE to set the RSE to a first resistive state, wherein the easy direction for programming the RSE comprises a second direction opposite the first direction in which a second write current is applied through the RSE to set the RSE to a different, second resistive state, and wherein the first write current is greater in magnitude than the second write current.

13. The method of claim 12 , wherein the switching device is connected in series with the RSE between a first control line and a second control line, wherein the easy direction for programming the unit cell corresponds to a respective sequencing of the RSE and the switching device such that the first write current passes from the first control line, through the RSE and then through the switching device to the second control line.

14. The method of claim 13 , wherein the hard direction for programming the unit cell corresponds to a respective physical orientation of the RSE and the switching device within the unit cell such that the second write current passes from the second control line, through the switching device and then through the RSE to the first control line.

15. The method of claim 10 , wherein the switching device comprises a transistor having a drain-to-source conductive path in series with the RSE, wherein in the hard direction for programming the unit cell a first write current passes through the drain-to-source conduction path prior to passing through the RSE, and wherein in the easy direction for programming the unit cell a second write current passes through the RSE prior to passing through the drain-to-source conduction path.

16. The method of claim 10 , wherein the RSE is characterized as a magnetic tunneling junction (MTJ) comprising a reference layer with a fixed direction of magnetization and a free layer with a selectively changeable direction of magnetization, wherein the MTJ is programmed to a first resistive state when the direction of magnetization of the free layer is set to be parallel to the direction of magnetization of the reference layer, wherein the MTJ is programmed to a second resistive state when a direction of magnetization of the free layer is set to be anti-parallel to the direction of magnetization of the reference layer, and wherein the MTJ is physically oriented within the unit cell with respect to the switching device such that a selected write current applied to the unit cell successively passes through the switching device, through the free layer and then through the reference layer.

17. The method of claim 10 , wherein the method further comprises prior steps of generating a mathematical model of the RSE, and using the mathematical model to identify the respective hard direction and easy direction for programming the RSE.

18. The method of claim 10 , wherein the RSE is characterized as a first RSE, and wherein the method further comprises prior steps of respectively passing write currents through a second RSE in opposing directions to respectively program the second RSE to different resistive states, identifying the hard direction for programming the first RSE as a direction of current flow through the second RSE that required a relatively greater write current, and identifying the easy direction for programming the first RSE as a direction of current flow through the second RSE that required a relatively lower write current.

19. The method of claim 10 , wherein the switching device is characterized as a metal oxide semiconductor field effect transistor (MOSFET).

20. The method of claim 10 , wherein the RSE is characterized as a resistive random access memory (RRAM) element.