Stressed semiconductor device and method for making
View Patent ↗A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.
1. A method of making a semiconductor device on a semiconductor layer, comprising:
forming a gate dielectric over the semiconductor layer;
forming a first layer of gate material over the gate dielectric;
etching the first layer of gate material to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion;
forming a storage layer over the select gate portion and over the first portion of the semiconductor layer;
forming a second layer of gate material over the storage layer;
etching the second layer of gate material to remove a first portion of the second layer of gate material over a first portion of the select gate portion; and
etching out a portion of the first portion of the select gate portion to leave an L-shaped select gate structure, wherein:
the L-shaped select gate structure has a vertical portion and a horizontal portion;
the vertical portion has a height and a width; and
the horizontal portion has a thickness that is less than the height of the vertical portion.
2. The method of claim 1 , wherein the step of etching out further comprises removing a portion of the storage layer over the first portion of the select gate structure.
3. The method of claim 1 , wherein the step of etching the second layer is further characterized as leaving a second portion of the second layer over the vertical portion and a third portion of the second layer over the first portion of the semiconductor layer.
4. The method of claim 1 , further comprising forming a stressor layer over the semiconductor device after the step of etching out.
5. The method of claim 4 , further comprising removing a portion of the horizontal portion of the L-shaped select gate structure to form a select gate comprising the vertical portion and a portion of the horizontal portion prior to the step of forming the stressor layer.
6. The method of claim 5 , wherein the step of etching the second layer of gate material is further characterized as forming a control gate from the second layer of gate material, the method further comprising implanting to form a first source/drain region in the semiconductor layer adjacent to the select gate and a second source/drain region in the semiconductor layer adjacent to the control gate.
7. The method of claim 6 , wherein the step of etching out is further characterized by the thickness of the horizontal layer being sufficiently thick to have implant blocking capability sufficient to prevent implants during the step of implanting if the implants are received directly by the horizontal layer.
8. The method of claim 6 , further comprising forming a sidewall spacer spanning the portion of the horizontal portion of the select gate to form a mask during at least a portion of the step of implanting.
9. The method of claim 8 , wherein the step of etching out is further characterized by the thickness of the horizontal portion being less than 60 nanometers.
10. The method of claim 6 , wherein the step of implanting includes forming sidewall spacers, the method further comprising:
forming silicide regions at a top surface of the first and second source/drain regions;
removing the sidewall spacers; and
forming a stressor layer over the select gate, control gate, and first and second source/drain regions.
11. The method of claim 1 , wherein the step of forming the storage layer is further characterized by the storage layer comprising nanocrystals.
12. The method of claim 1 , further comprising implanting the first layer of gate material with a dopant for use in making the first layer of gate material conductive.
13. The method of claim 1 , wherein the step of etching out is further characterized by the width of the vertical portion being less than 60 nanometers.
14. A semiconductor device, comprising:
a gate dielectric over a semiconductor layer;
an L-shaped select gate over the gate dielectric having a horizontal portion having a thickness and a vertical portion having a width and a height, the height greater than the thickness;
a control gate having a first portion over the vertical portion, a second portion laterally adjacent the vertical portion, and a third portion over the semiconductor layer; and
a storage layer between the control gate and the select gate and between the control gate and the semiconductor layer.
15. The semiconductor device of claim 14 , further comprising a stressor layer laterally adjacent to and over the control gate and laterally adjacent to and over the select gate.
16. The semiconductor device of claim 15 , further comprising:
a first source/drain in the semiconductor layer adjacent to the horizontal portion of the select gate; and
a second source/drain in the semiconductor layer laterally adjacent to the control gate,
wherein the stressor layer is over the first and second source/drains.
17. The semiconductor device of claim 14 , wherein the thickness of the horizontal portion is sufficiently thick to be able block source/drain implants.
18. The semiconductor device of claim 14 , wherein the thickness of the horizontal portion is less than 60 nanometers.
19. A method of making a semiconductor device on a semiconductor layer, comprising:
forming a select gate portion over the semiconductor layer;
forming a storage layer having a first portion over the select gate portion and a second portion over the semiconductor layer;
forming a control gate structure over the storage layer and having a first portion over a first portion of the select gate portion, a second portion laterally adjacent the select gate portion, and a third portion over the semiconductor layer;
removing a portion of the select gate portion to provide a select gate comprising a vertical portion under the first portion of the control gate and a horizontal portion extending away from the control gate, wherein the horizontal portion has a thickness less than a height of the vertical portion; and
forming an insulating layer that provides a stress to the semiconductor layer under the control gate and the select gate.
20. The method of claim 19 further comprising:
forming a first source/drain and a second source/drain in the semiconductor layer, wherein the first source/drain is adjacent to the select gate and the second source/drain is adjacent to the control gate.