Zener triggered ESD protection
View Patent ↗Electrostatic discharge (ESD) protection clamps ( 61, 95 ) for I/O terminals ( 22, 23 ) of integrated circuit (IC) cores ( 24 ) comprise a bipolar transistor ( 25 ) with an integrated Zener diode ( 30 ) coupled between the base ( 28 ) and collector ( 27 ) of the transistor ( 25 ). Prior art variations ( 311, 312, 313, 314 ) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants ( 781, 782 ) and forming the base ( 28, 68 ) coupled anode ( 301, 75 ) and collector ( 27, 70, 64 ) coupled cathode ( 302, 72 ) of the Zener ( 30 ) using opposed edges ( 713, 714 ) of a single relatively thin mask ( 71, 71″ ). The anode ( 301, 75 ) and cathode ( 302, 72 ) are self-aligned and the width ( 691 ) of the Zener space charge region ( 69 ) therebetween is defined by the opposed edges ( 713, 714 ) substantially independent of location and orientation of the ESD clamps ( 61, 95 ) on the die or wafer. Because the mask ( 71, 71″ ) is relatively thin and the anode ( 301, 75 ) and cathode ( 302, 72 ) implants ( 781, 782 ) relatively shallow, mask shadowing is negligible and prior art clamp voltage variations ( 311, 312, 313, 314 ) are avoided.
1. A method for forming an electrostatic discharge (ESD) protection clamp, comprising:
providing a supporting substrate having therein a semiconductor layer of a first conductivity type extending to a first surface of the substrate;
forming a well region of the first conductivity type in a first portion of the semiconductor layer and extending to the first surface;
forming a doped region of a second, opposite, conductivity type in the semiconductor layer extending substantially to the first surface and laterally spaced apart from the well region by a second portion of the semiconductor layer;
providing a mask layer having a portion of a predetermined width overlying part of the second portion of the semiconductor layer, the portion of the mask layer having a first edge facing toward the well region and a second edge facing toward the doped region;
using the portion of the mask layer, providing a still further doped region of the first conductivity type having a first portion ohmically coupled to the well region and a first distal edge substantially determined by the first edge of the mask portion; and
using the portion of the mask layer, providing an additional doped region of the second conductivity type having a first portion ohmically coupled to the doped region and a second distal edge substantially determined by the second edge of the mask portion.
2. The method of claim 1 , further comprising, forming an emitter region of the second conductivity type in the well region, spaced apart from the still further doped region.
3. The method of claim 2 , wherein the emitter region is laterally defined by an opening in the mask layer.
4. The method of claim 3 , wherein the emitter region and the additional doped region are formed at the same time.
5. The method of claim 1 further comprising, forming an ohmic contact region of the first conductivity type in the well region.
6. The method of claim 5 , wherein the ohmic contact region is laterally defined by another opening in the mask layer.
7. The method of claim 3 , wherein the ohmic contact region and the still further doped region are formed at the same time.
8. A method for forming an electrostatic discharge (ESD) protection clamp having first and second protective terminals adapted to limit a voltage appearing across a circuit core to which the protective terminals are coupled, comprising:
providing a supporting substrate;
forming a bipolar transistor on the substrate, wherein the bipolar transistor includes an emitter of a first conductivity type coupled to the first protective terminal, a collector of the first conductivity type coupled to the second protective terminal and a base of a second, opposite conductivity type located between the emitter and collector; and
forming an integrated Zener diode on the substrate, wherein the integrated Zener diode includes a first Zener terminal of the second conductivity type ohmically coupled to the base and a second Zener terminal of the first conductivity type ohmically coupled to the collector, and wherein, the first Zener terminal and the second Zener terminal are formed through openings on either side of a portion of a single mask such that separation of facing edges of the first Zener terminal and the second Zener terminal are substantially determined by opposed lateral edges of the single mask.
9. The method of claim 8 , wherein the first Zener terminal is more heavily doped than the base.
10. The method of claim 8 , wherein the second Zener terminal is spaced apart from the first Zener terminal by a further region of the second conductivity type.
11. The method of claim 10 , wherein the further region is less heavily doped than the base.
12. The method of claim 8 , further comprising forming a buried layer of the first conductivity type, underlying the base and coupled to the second Zener terminal.
13. The method of claim 12 , wherein the second Zener terminal comprises part of the collector terminal.
14. The method of claim 8 , wherein the single mask is an electrically conductive material separated from the first and second Zener terminals by an insulating region.
15. The method of claim 14 , further comprising forming an electrode adapted to function as a control electrode, wherein the electrode is electrically coupled to the electrically conductive material of the single mask.
16. The method of claim 8 , wherein the first and second Zener terminals are formed by ion implantation wherein a space charge region of the integrated Zener diode has a length substantially determined by a width of the single mask.
17. The method of claim 8 , wherein an upper surface of the single mask is separated from a surface a substrate in which the integrated Zener diode is formed by a thickness less than about 2.0 micrometers.
18. The method of claim 17 , wherein the thickness is less than about 0.5 micrometers.
19. A method for forming an electrostatic discharge (ESD) protection clamp having first and second terminals, comprising:
providing a supporting substrate;
forming a bipolar transistor on the substrate, wherein the bipolar transistor includes an emitter of a first conductivity type coupled to the first terminal, a collector of the first conductivity type coupled to the second terminal, and a base of a second, opposite, conductivity type; and
forming a Zener diode on the substrate coupled between the base and the collector, the Zener diode having a space charge region between a first doped region of the second conductivity type coupled to the base and a second doped region of the first conductivity type coupled to the collector, the space charge region having a substantially predetermined width defined by opposed edges of a portion of a single mask.
20. The method of claim 19 , wherein the single mask comprises a conductor coupled to a further terminal and insulated from the space charge region and adapted to modulate a trigger voltage of the Zener diode in response to a voltage applied to the further terminal.