Multiple-level memory cells and error detection
View Patent ↗Memory, modules and methods for using error detection with multi-level memory cells where the number of storage levels of the memory cells is an integer power of a non-binary prime number are provided. Additional circuit and methods are disclosed.
1. A method comprising:
adjusting an error detection operation in relation to a write operation of data into a multi-level memory cell, wherein the adjusting comprises adjusting an error correction code (ECC) overhead value based on a number of error correction memory cells, a number of storage levels in the multi-level memory cell being a non-binary number; and
detecting a possible error in read data during a successive read operation of the data from the multi-level memory cell.
2. The method of claim 1 , wherein each of the storage levels includes at least one of a voltage level, magnetic flux level, or a phase of a material.
3. The method of claim 1 , wherein a base-p logarithm of the number of the storage levels comprises an integer greater than zero where p is a prime number other than 2.
4. The method of claim 1 , wherein detecting the possible error comprises detecting the possible error using at least one code, the at least one code comprising:
at least one of a finite field algebra code, a BCH (Bose, Ray-Chaudhuri, and Hocquenghem) code, a LDPC (low density parity check) code, a majority logic decodable code, or a geometry code.
5. The method of claim 1 , further comprising:
generating encoded digital data including the data and one or more check symbols.
6. The method of claim 5 , further comprising:
converting the encoded digital data into a quantity that indicates storage levels of the memory cell that is engaged during the write operation.
7. The method of claim 1 , wherein detecting the possible error comprises:
converting a quantity corresponding to a number of storage levels read from the memory cell, during the successive read operation, into corresponding encoded digital data.
8. The method of claim 7 , further comprising:
decoding the encoded digital data to retrieve read data and one or more read check symbols and verifying correctness of the read data based on the one or more read check symbols.
9. The method of claim 8 , further comprising:
using at least one code to correct an error in the read data from the memory cell.
10. Memory comprising:
a memory cell within a memory array, the memory cell to store a number of bits of data, the number of bits of data being determined by a non-binary number of storage levels in the memory cell; and
a logic module to detect and correct errors in read data, wherein the logic module comprises an adjustment module to adjust an error correction code (ECC) overhead value, wherein the ECC overhead value is at least partially determined based on a number of error correction memory cells.
11. The memory of claim 10 , wherein the logic module comprises circuits including at least one of:
logic gates or circuits to implement look-up tables, or
read only memory (ROM), random Access memory (RAM) or nonvolatile memory to store look-up tables.
12. The memory of claim 10 , wherein the logic module is integrated with the memory array in at least one of a single die, a multi-die package, or a multi-package die.
13. The memory of claim 10 , wherein the logic module is configured to implement at least one of a finite field algebra code, a BCH (Bose, Ray-Chaudhuri, and Hocquenghem) code, a LDPC (low density parity check) code, a majority logic decodable code, or a geometry code.
14. The memory of claim 13 , wherein the finite field algebra code comprises a systematic code that generates coded data including a verbatim copy of payload data.
15. The memory of claim 10 , wherein the logic module comprises:
an encoder module to generate encoded digital data including the one or more bits of data and one or more check symbols.
16. The memory of claim 15 , wherein the logic module comprises:
an analog-to-digital converter (ADC) module to convert the encoded digital data into a quantity that indicates storage levels of the memory cell that is engaged during the write operation.
17. The memory of claim 10 , wherein the logic module comprises:
a digital-to-analog converter (DAC) module to convert a quantity corresponding to a number of storage levels read from the memory cell, during the successive read operation, into corresponding encoded digital data.
18. The memory of claim 17 , wherein the logic module comprises:
a decoder module to decode the encoded digital data to retrieve one or more bits of read data and one or more read check symbols and to verify correctness of the one or more bits of read data based on the one or more read check symbols.
19. The memory of claim 10 , wherein the memory array includes at least one of:
an analog-to-digital converter (ADC) module to convert an encoded digital data into a quantity that indicates storage levels of the memory cell that is engaged during the write operation; or
a digital-to-analog converter (DAC) module to convert a quantity corresponding to a number of storage levels read from the memory cell, during the successive read operation, into corresponding encoded digital data.
20. The memory of claim 10 , wherein the logic module comprises:
an error correction module to implement, at least partially, at least one error detection and correction algorithm to correct one or more errors in data read from the memory cell.
21. Memory comprising:
a plurality of memory cells, each memory cell to store one or more bits of data to be retained in at least one of non-binary number of storage levels;
a digital to analog converter (DAC) module to convert encoded digital data including the one or more bits of data and one or more check symbols into a corresponding quantity to be stored into memory cells of the memory in a write operation, the first encoded digital data including the one or more bits of data and the one or more check symbols;
an analog to digital converter (ADC) module to convert a quantity read from the memory cells of memory into second encoded digital data including one or more read bits of data and one or more read check symbols in a successive read operation;
an error correction module to detect a possible error in one or more bits of read data based on the read check symbols and to correct the possible error using a code; and
an adjustment module to adjust an error correction code (ECC) overhead value, wherein the ECC overhead value is at least partially determined based on a number of error correction memory cells.
22. The memory of claim 21 , comprising:
an encoder module to generate the first encoded digital data based on the one or more bits of data and the one or more check symbols.
23. The memory of claim 21 , comprising:
a decoder module to decode the second encoded digital data to retrieve the one or more bits of read data and the one or more read check symbols.
24. A module comprising:
an encoder module to generate first encoded digital data based on one or more bits of data and one or more check symbols;
a digital-to-analog converter (DAC) module to convert the first encoded digital data into a corresponding quantity to be stored into a memory cell in a write operation, the memory cell having a non-binary number of storage levels wherein the base-p logarithm of the number of storage levels is an integer greater than zero where p is a prime number other than 2;
an analog to digital converter (ADC) module to convert a quantity read from the memory cell into second encoded digital data including one or more bits of read data and one or more read check symbols in a successive read operation;
an error correction module to detect a possible error in the one or more bits of read data based on the read check symbols and to correct the possible error using a code; and
an adjustment module to adjust an error correction code (ECC) overhead value, wherein the ECC overhead value is determined at least based on a number of error correction memory cells.