Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure
View Patent ↗A semiconductor device ( 1 ) and a method are disclosed for obtaining on a substrate ( 2 ) a multilayer structure ( 3 ) with a quantum well structure ( 4 ). The quantum well structure ( 4 ) comprises a semiconductor layer ( 5 ) sandwiched by insulating layers ( 6,6′ ), wherein the material of the insulating layers ( 6,6′ ) has preferably a high dielectric constant. In a FET the quantum wells ( 4,9 ) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.
1. A method of manufacturing comprising the steps of:
forming a first quantum well structures by
forming a layer of electrically insulating material,
forming a layer of semiconductor material, characterized in that the layer of insulating material and the layer of semiconductor material are grown epitaxially on top of each other; and
forming a second quantum well structure at a distance from the first quantum well whereby at least one of the quantum wells functions as a gate for the other quantum well.
2. The method as claimed in claim 1 , wherein a further layer of electrically insulating material is grown epitaxially on the layer of semiconductor material.
3. The method as claimed in claim 1 , wherein the steps of forming the first quantum well structure are repeated at least two times.
4. The method as claimed in claim 1 , wherein the material of the electrically insulating layer is a high-k dielectric having a dielectric constant larger than 3.9.
5. The method as claimed in claim 1 , wherein the electrically insulating layer is formed with molecular beam epitaxy.
6. The method as claimed in claim 1 , wherein the electrically insulating layer is in-situ annealed.
7. The method as claimed in claim 4 , characterized in that the material of the high-k dielectric comprises yttrium.
8. The method as claimed in claim 1 , wherein the semiconductor layer comprises silicon or a silicon-germanium compound.
9. A method of manufacturing a semiconductor device, comprising,
manufacturing a quantum well structure on a substrate, the method including,
forming a layer of electrically insulating material, and
forming a layer of semiconductor material, characterized in that the layer of insulating material and the layer of semiconductor material are grown epitaxially on top of each other,
forming a gate dielectric on the quantum well structure,
forming a gate, and
forming a source region and a drain region by bringing doping atoms into the quantum well structure self aligned to the gate to a depth of at least the total thickness at least one of the quantum well structures.