Semiconductor device
View Patent ↗The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
1. A semiconductor device including a DC-DC converter, comprising:
a first semiconductor chip including a high-side MOSFET of the DC-DC converter, the high-side MOSFET including a source, a gate and a drain;
a second semiconductor chip including a low-side MOSFET of the DC-DC converter, the low-side MOSFET including a source, a gate and a drain;
a third semiconductor chip including a driver circuit to drive a gate of the high-side MOSFET and a gate of the low-side MOSFET;
a resin encapsulator encapsulating the first, second and third semiconductor chips;
an input power supply terminal, exposed from the resin encapsulator, for supplying an input power to the DC-DC converter;
a reference potential supply terminal, exposed from the resin encapsulator, for supplying a reference potential to the DC-DC converter; and
an output terminal exposed from the resin encapsulator, for outputting an output of the DC-DC converter,
wherein the high-side MOSFET and the low-side MOSFET are electrically coupled in series between the input power supply terminal and the reference potential supply terminal,
wherein a source-to-drain path of the high-side MOSFET is electrically coupled in series between the input power supply terminal and the output terminal,
wherein a source-to-drain path of the low-side MOSFET is electrically coupled in series between the reference potential supply terminal and the output terminal, and
wherein the first semiconductor chip and the second semiconductor chip are electrically and mechanically coupled to a metal material which is electrically coupled to the output terminal.
2. A semiconductor device according to claim 1 ,
wherein the metal material is comprised of copper.
3. A semiconductor device according to claim 1 ,
wherein the first semiconductor chip and the second semiconductor chip are coupled to the metal material via paste.
4. A semiconductor device according to claim 1 ,
wherein the resin encapsulator includes a top surface and a bottom surface opposite the top surface, and
wherein the input power supply terminal, the reference potential supply terminal and the output terminal are exposed from the bottom surface of the resin body.
5. A semiconductor device according to claim 4 ,
wherein the first semiconductor chip includes a source electrode pad which is electrically coupled to the source of the high-side MOSFET, and
wherein the source electrode pad faces toward the top surface of the resin encapsulator.
6. A semiconductor device according to claim 1 ,
wherein the second semiconductor chip includes a drain electrode which is electrically coupled to the drain of the low-side MOSFET, and
wherein the drain electrode is mechanically coupled to the metal material.
7. A semiconductor device according to claim 1 ,
wherein the gate of the high-side MOSFET is electrically coupled to the driver circuit via a first wire, and
wherein the gate of the low-side MOSFET is electrically coupled to the driver circuit via a second wire.
8. A semiconductor device according to claim 7 ,
wherein the first semiconductor chip has a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and
wherein the first wire is disposed so as to overlap one of the short sides of the first semiconductor chip.
9. A semiconductor device according to claim 1 ,
wherein the first semiconductor chip has a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and
wherein one of said long sides of the first semiconductor chip is arranged such that a closest distance between the second semiconductor chip and said one long side is less than a closest distance between the second semiconductor chip and the other long side.
10. A semiconductor device including a DC-DC converter, comprising:
a first semiconductor chip including a first MOSFET of the DC-DC converter, the first MOSFET including a source, a gate and a drain;
a second semiconductor chip including a second MOSFET of the DC-DC converter, the second MOSFET including a source, a gate and a drain;
a third semiconductor chip including a driver circuit to drive a gate of the first MOSFET and a gate of the second MOSFET;
a resin encapsulator encapsulating the first, second and third semiconductor chips;
an input power supply terminal, exposed from the resin encapsulator, for supplying an input power to the DC-DC converter;
a reference potential supply terminal, exposed from the resin encapsulator, for supplying a reference potential to the DC-DC converter;
an output terminal exposed from the resin encapsulator, for outputting an output of the DC-DC converter;
wherein the first MOSFET and the second MOSFET are electrically coupled in series between the input power supply terminal and the reference potential supply terminal,
wherein a source-to-drain path of the first MOSFET is electrically coupled in series between the input power supply terminal and the output terminal,
wherein a source-to-drain path of the second MOSFET is electrically coupled in series between the reference potential supply terminal and the output terminal, and
wherein the first semiconductor chip and the second semiconductor chip are electrically and mechanically coupled to a metal material which is electrically coupled to the output terminal.
11. A semiconductor device according to claim 8 ,
wherein the metal material is comprised of copper.
12. A semiconductor device according to claim 8 ,
wherein the first MOSFET is comprised of a p channel MOSFET, and
wherein the second MOSFET is comprised of an n channel MOSFET.
13. A semiconductor device according to claim 8 ,
wherein the first MOSFET includes a first drain electrode which is electrically coupled to the drain of the first semiconductor chip,
wherein the second MOSFET includes a second drain electrode which is electrically coupled to the drain of the second semiconductor chip, and
wherein the first and second drain electrodes are mechanically coupled to the metal material.
14. A semiconductor device according to claim 8 ,
wherein the resin encapsulator includes a top surface and a bottom surface opposite the top surface, and
wherein the input power supply terminal, the reference potential supply terminal and the output terminal are exposed from the bottom surface of the resin body.
15. A semiconductor device according to claim 14 ,
wherein the first MOSFET includes a first source electrode pad which is electrically coupled to the source of the first semiconductor chip,
wherein the second MOSFET includes a second source electrode pad which is electrically coupled to the source of the second semiconductor chip, and
wherein the first and second source electrode pads faces toward the top surface of the resin encapsulator.
16. A semiconductor device according to claim 1 , wherein the metal material comprises a common die pad on which both the first semiconductor chip and the second semiconductor chip are mounted to thereby be electrically and mechanically coupled to the common die pad.
17. A semiconductor device according to claim 10 , wherein the metal material comprises a common die pad on which both the first semiconductor chip and the second semiconductor chip are mounted to thereby be electrically and mechanically coupled to the common die pad.