Ternary content addressable memory having reduced leakage effects
View Patent ↗A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced.
1. A memory system comprising:
a plurality of ternary content addressable memory (TCAM) cells arranged in a column, each TCAM cell including at least one memory cell and match logic;
wherein each memory cell of a first set of the TCAM cells in the column has a first layout, and each memory cell of a second set of the TCAM cells in the column has a second layout, the second layout being a mirror image about a vertical axis of the first layout, and wherein the match logic of each TCAM cell has the same layout as each other; and
a bit line pair connected to each of the plurality of TCAM cells, wherein data is written to and read from the TCAM cells on the bit line pair.
2. The memory system of claim 1 , further comprising a write decoder logic coupled to receive a write data value and a write address value, wherein the write decoder logic (i) inverts the write data value if a write operation accesses a TCAM cell in the first set of TCAM cells, and (ii) does not invert the write data value if a write operation accesses a TCAM cell in the second set of TCAM cells.
3. The memory system of claim 1 , further comprising a read decoder logic coupled to receive a read data value provided on the bit line pair and a read address value, wherein the read decoder logic (i) inverts the read data value if a read operation accesses a TCAM cell in the first set of TCAM cells, and (ii) does not invert the read data value if a read operation accesses a TCAM cell in the second set of TCAM cells.
4. A method comprising:
writing data to a column of ternary content addressable memory (TCAM) cells via a bit line pair, each TCAM cell including at least one memory cell and match logic, wherein each memory cell of a first set of TCAM cells in the column has a first layout, and each memory cell of a second set of TCAM cells in the column has a second layout, the second layout being a mirror image about a vertical axis of the first layout, and wherein the match logic of each TCAM cell has the same layout as each other;
wherein the first set of TCAM cells are written with a first bit line polarity, and the second set of TCAM cells are written with a second bit line polarity, the second bit line polarity being opposite the first bit line polarity; and
reading data from the column of TCAM cells via the bit line pair, wherein the first set of the TCAM cells are read with the first bit line polarity, and the second set of the TCAM cells are read with the second bit line polarity.
5. The method of claim 4 , wherein writing data to a column of TCAM cells includes determining whether the write operation will be performed in the first set of TCAM cells or the second set of TCAM cells.
6. The method of claim 4 , wherein reading data from the column of TCAM cells includes determining whether the read operation will be performed in the first set of TCAM cells or the second set of TCAM cells.
7. The memory system of claim 1 , further comprising a search line pair connected to each of the plurality of TCAM cells, wherein search data is provided to the TCAM cells on the search line pair.
8. The memory system of claim 1 , wherein each of the plurality of TCAM cells comprises a first memory circuit coupled to the bit line pair, and a second memory circuit coupled to the bit line pair.
9. The memory system of claim 8 , wherein the first and second memory circuits are static random access memory (SRAM) cells, each having a pair of access transistors coupled to the bit line pair.
10. The memory system of claim 2 , wherein the write decoder logic comprises an exclusive OR circuit.
11. The memory system of claim 3 , wherein the read decoder logic comprises an exclusive OR circuit.