Fabrication method of semiconductor integrated circuit device
View Patent ↗In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.
1. A method of fabricating a semiconductor device, comprising the steps of:
(a) preparing a wiring substrate having plural wiring patterns, pad patterns, and a solder resist layer on one surface thereof, said plural wiring patterns being covered by said solder resist layer, said pad patterns being exposed from by said solder resist layer;
(b) configuring a reference plane over said pad patterns by subjecting said wiring substrate to a three-dimensional measurement, to measure an actual height of solder which is to be formed on each of said pad patterns in a subsequent process;
(c) after the step (b), printing solder on said wiring substrate, to form solder patterns on said pad patterns respectively;
(d) after the step (c), inspecting height of said solder patterns printed over the substrate with reference to said reference plane; and
(e) after the step (d), mounting circuit parts over said one surface of said wiring substrate by using said solder patterns.
2. A method of fabricating a semiconductor device according to claim 1 , wherein said reference plane corresponds to an upper surface of said solder resist layer.
3. A method of fabricating a semiconductor device according to claim 2 , wherein said solder resist layer has a first portion and a second portion,
wherein said first and second portions have different heights from upper surfaces of said pad patterns corresponding to said first and second portions of said solder resist layer respectively, and
wherein said reference plane includes said different heights.
4. A method of fabricating a semiconductor device according to claim 3 , wherein said circuit parts include a semiconductor package.
5. A method of fabricating a semiconductor device according to claim 4 , wherein said semiconductor package has a plurality of leads, and wherein the step (e) includes subjecting said wiring substrate to a heat treatment to solder said plurality of leads of said semiconductor package to said pad patterns of said wiring substrate.
6. A method of fabricating a semiconductor device, comprising the steps of:
(a) preparing a wiring substrate having plural wiring patterns, pad patterns, and a solder resist layer on one surface thereof, using a wiring substrate fabrication system, said plural wiring patterns being covered by said solder resist layer, said pad patterns being exposed from by said solder resist layer;
(b) configuring a reference plane over said pad patterns by subjecting said wiring substrate to a three-dimensional measurement by a 3D measurement system, to measure an actual height of solder which is to be formed on each of said pad patterns in a subsequent process;
(c) after the step (b), printing solder on said wiring substrate by a solder printing system, to form solder patterns on said pad patterns respectively;
(d) after the step (c), inspecting height of said solder patterns printed over the substrate with reference to said reference plane, using an inspection apparatus; and
(e) after the step (d), and utilizing a circuit part mounting system, mounting circuit parts over said one surface of said wiring substrate using said solder patterns.