Switchable memory diode—a new memory device
View Patent ↗Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.
1. A method comprising:
forming, in each memory cell of an array of memory cells, a passive layer adjacent to a first ohmic contact layer;
forming an active layer adjacent to the passive layer, wherein
one of the active layer and the passive layer is composed of a P-type material and one of the active layer and the passive layer is composed of an N-type material such that combining the layers forms a diodic junction; and
forming a second ohmic contact layer adjacent to the active layer.
2. The method of claim 1 , further comprising:
forming electrode contacts at the first and second ohmic contact layers.
3. The method of claim 1 , further comprising:
forming the active layer via a chemical vapor deposition (CVD) process.
4. The method of claim 1 , further comprising:
forming the active layer via a gas phase reaction process.
5. The method of claim 1 , further comprising:
forming the active layer via a spin coating process.
6. The method of claim 1 , further comprising:
forming the active layer via a liquid phase reaction process.
7. The method of claim 1 , further comprising:
forming the first and second ohmic contact layers via a deposition process comprising at least one of: vacuum thermal evaporation, sputtering, or plasma enhanced chemical vapor deposition (PECVD) utilizing a metal organic (MO) precursor.
8. The method of claim 1 , further comprising:
forming the passive layer via a deposition process comprising at least one of: thermal deposition, physical vapor deposition (PVD), non-selective chemical vapor deposition (CVD), or complete sulfidation of a pre-deposited thin copper layer.
9. The method of claim 1 , wherein forming the active layer comprises:
depositing a conductivity facilitating compound on the passive layer.
10. A method comprising:
forming a first electrode on a substrate associated with a memory device;
forming a passive layer on the first electrode;
forming an active layer on the passive layer, wherein
one of the active layer and the passive layer is composed of a P-type material and one of the active layer and the passive layer is composed of an N-type material such that combining the layers forms a diodic junction; and
forming a second electrode on the active layer.
11. The method of claim 10 , further comprising:
doping the active layer to adjust threshold properties of the diodic p/n junction.
12. The method of claim 10 , further comprising:
forming ohmic contact layers at the first and second electrodes.
13. The method of claim 12 , further comprising:
depositing the passive layer upon an ohmic contact layer via at least one of:
vacuum thermal evaporation, sputtering, or plasma enhanced chemical vapor deposition (PECVD) utilizing a metal organic (MO) precursor.
14. The method of claim 10 , further comprising:
depositing a conductivity facilitating compound on the passive layer.
15. The method of claim 10 , further comprising:
forming the active layer via at least one of:
a chemical vapor deposition (CVD) process;
a gas phase reaction process;
a spin coating process; or
a liquid phase reaction process.
16. The method of claim 10 , further comprising:
forming the passive layer via a deposition process comprising at least one of: thermal deposition, physical vapor deposition (PVD), non-selective chemical vapor deposition (CVD), or complete sulfidation of a pre-deposited thin copper layer.