Semiconductor memory device and a method of manufacturing the same
A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
1. A semiconductor integrated circuit device comprising:
a first MISFET including having a first gate electrode formed over a main surface of a semiconductor substrate, and further including a first semiconductor region and a second semiconductor region formed in the semiconductor substrate;
a first interlayer insulating film formed over the first MISFET and having an opening;
a conductive film formed within the opening;
a first vertical MISFET formed over the conductive films
the first vertical MISFET including a source region and a drain region which are formed in a laminate,
the laminate extending in a perpendicular direction from the main surface such that the source region and the drain region are perpendicularly laminated,
the laminate electrically connected to the first semiconductor region through the conductive film and disposed over the first semiconductor region such that the laminate overlaps, in a plane view, with the first semiconductor region,
the first vertical MISFET further including a gate electrode formed via a gate insulating film on a side wall of the laminate; and
a word line formed over first interlayer insulating film and electrically connected to the gate electrode of the first vertical MISFET.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the word line extends in a first direction and is electrically connected to a plurality of memory cells arranged in the first direction.
3. The semiconductor integrated circuit device according to claim 2 ,
wherein a channel forming region of the first MISFET is arranged, in a second direction crossing the first direction, between the first semiconductor region and the second semiconductor region.
4. The semiconductor integrated circuit device according to claim 2 , further comprising:
a first wiring line formed over the laminate and electrically connected to the laminate,
the first wiring line extending in a second direction crossing the first direction and electrically connected to a plurality of memory cells arranged in the second direction.
5. The semiconductor integrated circuit device according to claim 1 , further comprising:
a first wiring line formed over the laminate and electrically connected to the laminate; and
a second wiring line formed below the laminate and electrically connected to the second semiconductor region.
6. The semiconductor integrated circuit device according to claim 1 , further comprising:
a first wiring line formed over the laminate and electrically connected to the laminate.
7. The semiconductor integrated circuit device according to claim 1 ,
wherein the conductive film is comprised of a metal film, and
wherein the laminate is comprised of silicon material.
8. The semiconductor integrated circuit device according to claim 1 , further comprising:
an oxidation-resistant conductive film providing electrical connection between the laminate and the conductive film,
the oxidation-resistant conductive film is formed below the laminate and over the conductive film.
9. A semiconductor integrated circuit device comprising:
a first MISFET including a first gate electrode formed over a main surface of a semiconductor substrate, and further including a first semiconductor region and a second semiconductor region formed in the semiconductor substrate;
a first interlayer insulating film formed over the first MISFET and having an opening;
a conductive film formed within the opening;
a first vertical MISFET formed over the conductive film,
the first vertical MISFET including a source region and a drain region which are formed in a laminate,
the laminate extending in a perpendicular direction from the main surface such that the source region and the drain region are perpendicularly laminated,
the laminate electrically connected to the first semiconductor region through the conductive film and disposed over the first semiconductor region such that the laminate overlaps, in a plane view, with the first semiconductor region,
the first vertical MISFET further including a gate electrode formed via a gate insulating film on a side wall of the laminate;
a word line formed over first interlayer insulating film and electrically connected to the gate electrode of the first vertical MISFET;
a first wiring line formed below the laminate and electrically connected to the second semiconductor region through a plug;
a second wiring line formed with the same level layer as the first wiring line; and
a second MISFET for a peripheral circuit including a second gate electrode formed over the main surface,
the second gate electrode electrically connected to the second wiring line through a plug.
10. The semiconductor integrated circuit device according to claim 9 ,
wherein the word line extends in a first direction and is electrically connected to a plurality of memory cells arranged in the first direction.
11. The semiconductor integrated circuit device according to claim 10 ,
wherein a channel forming region of the first MISFET is arranged, in a second direction crossing the first direction, between the first semiconductor region and the second semiconductor region.
12. The semiconductor integrated circuit device according to claim 10 , further comprising:
a third wiring line formed over the laminate and electrically connected to the laminate,
the third wiring line extending in a second direction crossing the first direction and electrically connected to a plurality of memory cells arranged in the second direction.
13. The semiconductor integrated circuit device according to claim 9 , further comprising:
a third wiring line formed over the laminate and electrically connected to the laminate;
a fourth wiring line formed below the laminate and electrically connected to the second semiconductor region.
14. The semiconductor integrated circuit device according to claim 9 , further comprising:
a third wiring line formed over the laminate and electrically connected to the laminate.
15. The semiconductor integrated circuit device according to claim 9 ,
wherein the conductive film is comprised of a metal film, and
wherein the laminate is comprised of silicon material.
16. The semiconductor integrated circuit device according to claim 9 , further comprising:
an oxidation-resistant conductive film providing electrical connection between the laminate and the conductive film,
the oxidation-resistant conductive film is formed below the laminate and over the conductive film.