IP Library Granted Patent US 7,977,189
Granted Patent B2
US 7,977,189 · App. 12/502,891 · Granted Jul 12, 2011

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 7,977,189
App. No.
12/502,891
Granted
Jul 12, 2011
Kind
B2
Abstract

The present invention relates to a semiconductor device that includes a semiconductor substrate ( 10 ) having source/drain diffusion regions ( 14 ) formed therein and control gates ( 20 ) formed thereon, with grooves ( 18 ) being formed on the surface of the semiconductor substrate ( 10 ) and being located below the control gates ( 20 ) and between the source/drain diffusion regions ( 14 ). The grooves ( 18 ) are separated from the source/drain diffusion regions ( 14 ), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.

Claims (33)

1. A method of manufacturing a semiconductor device, comprising:

forming a groove on a semiconductor substrate, the groove formed therein to extend in a first direction, wherein forming the groove comprises:

forming a silicon oxide film in a surface of the semiconductor substrate;

forming an insulating film having an opening on the semiconductor substrate with a sidewall formed around the opening;

forming source/drain diffusion regions between which the groove is located, the source/drain diffusion regions formed therein to extend in the first direction, wherein forming the source/drain diffusion regions comprises implanting ions in the semiconductor substrate, with a mask being formed with the silicon oxide film and the sidewall;

forming an ONO film on the semiconductor substrate over the groove and the source/drain regions; and

forming a control gate on the ONO film, the control gate formed therein to extend in a second direction perpendicular to the first direction, the control gate provided over portions of the groove and the source/drain regions.

2. The method as claimed in claim 1 , wherein forming the groove further comprises:

thermally oxidizing a surface of the semiconductor substrate to form the silicon oxide film; and

removing the silicon oxide film.

3. The method as claimed in claim 2 ,

wherein thermally oxidizing the surface of the semiconductor substrate utilizes the insulating film and the sidewall as a mask.

4. The method as claimed in claim 3 , wherein the insulating film is formed with silicon nitride film, and wherein the sidewall is formed with silicon oxide film.

5. The method as claimed in claim 1 , wherein the groove is formed below the control gate and between the source/drain regions.

6. The method as claimed in claim 5 , wherein the groove is separated from the source/drain regions by a predetermined distance.

7. The method as claimed in claim 1 , wherein the source/drain diffusion regions are formed self-aligned with the groove.

8. The method as claimed in claim 1 , wherein forming the groove comprises etching.

9. The method as claimed in claim 1 , wherein the groove is formed a distance equivalent to the width of each sidewall from each adjacent source/drain region.

10. A method of manufacturing a semiconductor device, comprising:

forming a groove on a semiconductor substrate, the groove formed therein to extend in a first direction;

forming source/drain diffusion regions between which the groove is located, the source/drain diffusion regions formed therein to extend in the first direction, wherein the groove is separated from the source/drain diffusion regions by a distance equivalent to a width of sidewalls formed around an opening in an insulating film formed on the semiconductor substrate, the sidewalls serving as a mask during the source/drain diffusion region formation;

forming an ONO film on the semiconductor substrate over the groove and the source/drain regions; and

forming a control gate on the ONO film, the control gate formed therein to extend in a second direction perpendicular to the first direction, the control gate provided over portions of the groove and the source/drain regions.

11. The method as claimed in claim 10 , wherein forming the groove comprises:

thermally oxidizing a surface of the semiconductor substrate to form a silicon oxide film; and

removing the silicon oxide film.

12. The method as claimed in claim 11 , wherein thermally oxidizing the surface of the semiconductor substrate utilizes the insulating film and the sidewall as a mask.

13. The method as claimed in claim 12 , wherein forming the source/drain diffusion regions comprises implanting ions in the semiconductor substrate, with a mask being formed with the silicon oxide film and the sidewall.

14. The method as claimed in claim 12 , wherein the insulating film is formed with silicon nitride film, and wherein the sidewall is formed with silicon oxide film.

15. The method as claimed in claim 10 , wherein the groove is formed below the control gate and between the source/drain regions.

16. The method as claimed in claim 15 , wherein the groove is separated from the source/drain regions by a predetermined distance.

17. The method as claimed in claim 10 , wherein the source/drain diffusion regions are formed self-aligned with the groove.

18. The method as claimed in claim 10 , wherein the step of forming the groove comprises etching.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0337 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →